Crystal-to-0.7V Differential HCSL/
LVCMOS Frequency Synthesizer
841S012DI
Datasheet
G
ENERAL
D
ESCRIPTION
The 841S012DI is an optimized PCIe, sRIO and Gigabit Ethernet
Frequency Synthesizer and a member of high performance clock
solutions from IDT. The 841S012DI uses a 25MHz parallel resonant
crystal to generate 33.33MHz - 200MHz clock signals, replacing
multiple oscillators and fanout buffer solutions. The device supports
±0.25% center-spread, and -0.5% down-spread clocking with two
spread select pins (SSC[1:0]). The VCO operates at a frequency of
2GHz. The device has three output banks: Bank A with two 100MHz
– 250MHz HCSL outputs; Bank B with seven 33.33MHz – 200MHz
LVCMOS/ LVTTL outputs; and Bank C with one 33.33MHz – 200MHz
LVCMOS/LVTTL output.
All Banks A, B and C have their own dedicated frequency
select pins and can be independently set for the frequencies
mentioned above. The low jitter characteristic of the 841S012DI
makes it an ideal clock source for PCIe, sRIO and Gigabit Ethernet
applications. Designed for networking and industrial applications,
the 841S012DI can also drive the high-speed clock inputs of com-
munication processors, DSPs, switches and bridges.
F
EATURES
• Two 0.7V differential HCSL outputs (Bank A), configurable for
PCIe (100MHz or 250MHz) and sRIO (100MHz or 125MHz)
clock signals
Eight LVCMOS/LVTTL outputs (Banks B/C),
18Ω typical output impedance
Two REF_OUT LVCMOS/LVTTL clock outputs,
23Ω typical output impedance
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or one LVCMOS/LVTTL single-ended refer-
ence clock input
• Supports the following output frequencies:
HCSL Bank A:
100MHz, 125MHz, 200MHz and 250MHz
LVCMOS/LVTTL Bank B/C:
33.33MHz, 50MHz, 66.67MHz,
100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz
• VCO: 2GHz
• Spread spectrum clock: ±0.25% center-spread (typical) and
-0.6% down-spread (typical)
• PLL bypass and output enable
• RMS period jitter: 10ps (typical), QAx/nQAx outputs
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
P
IN
A
SSIGNMENT
V
DDOB
QB6
GND
QB5
V
DDOB
QB4
GND
QB3
V
DDOB
QB2
GND
QB1
QB0
56 55 54 53 52 51 50 49 48 47 46 45 44 43
V
DD_REFOUT
REF_OUT0
REF_OUT1
GND
GND
REF_IN
V
DD
REF_SEL
XTAL_IN
XTAL_OUT
BYPASS
REF_OE
nMR
V
DD
1
2
3
4
5
6
7
8
9
10
11
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
DDOC
QC
GND
QBC_OE
V
DDA
V
DDA
GND
GND
IREF
QA0
nQA0
QA1
nQA1
V
DD
ICS841S012DI
56-Lead VFQFN
8mm x 8mm x 0.925mm
package body
K Package
Top View
12
13
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
F_SELB2
F_SELB1
F_SELB0
F_SELC2
F_SELC1
F_SELC0
F_SELA1
F_SELA0
QA_OE
SSC1
SSC0
©2016 Integrated Device Technology, Inc
1
GND
V
DD
GND
V
DDOB
January 4, 2016
841S012DI Datasheet
B
LOCK
D
IAGRAM
QA_OE
Pullup
F_SELA[1:0]
Pulldown
2
QA0
BYPASS
XTAL_IN
Pulldown
nQA0
÷NA
QA1
nQA1
25MHz
OSC
XTAL_OUT
0
1
PLL
VCO
2GHz
0
Pulldown
QB0
REF_IN
1
QB1
QB2
REF_SEL
Pulldown
M =
÷
80
QB3
÷NB
QB4
F_SELB[2:0]
Pulldown
3
QB5
IREF
QB6
÷NC
F_SELC[2:0]
nMR
QBC_OE
SSC[1:0]
Pulldown
Pullup
Pullup
Pullup
2
3
QC
Spread
Spectrum
REF_OUT0
REF_OUT1
REF_OE
Pulldown
©2016 Integrated Device Technology, Inc
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January 4, 2016
841S012DI Datasheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
7, 14, 28, 29
2,
3
4, 5, 15, 27, 35,
36, 40, 46, 50,
54
6
8
9,
10
11
12
Name
V
DD_REFOUT
V
DD
REF_OUT0,
REF_OUT1
GND
REF_IN
REF_SEL
XTAL_IN, XTAL_
OUT
BYPASS
REF_OE
Power
Power
Output
Power
Input
Input
Input
Input
Input
Type
Description
Output supply pin for REF_OUT.
Core supply pins.
Single-ended LVCMOS/LVTTL reference clock outputs.
23Ω typical output impedance.
Power supply ground.
Pulldown Single-ended LVCMOS/LVTTL reference clock input.
Reference select pin. When HIGH selects REF_IN. When LOW,
selects crystal. LVCMOS/LVTTL interface levels. See Table 3E.
Crystal oscillator interface. XTAL_OUT is the output. XTAL_IN is the input.
External tuning capacitor must be used for proper operation.
When HIGH bypasses PLL. When LOW, selects PLL.
Pulldown
LVCMOS/LVTTL interface levels. See Table 3J.
Active HIGH REF_OUT enables/disables pin.
Pulldown
LVCMOS/LVTTL interface levels. See Table 3H.
Active LOW Master Reset. When logic LOW, the internal dividers are reset
and the outputs are in high impedance (HI-Z). When logic HIGH, the internal
Pullup
dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels. See Table 3I.
Pulldown
Pullup
Pulldown
SSC control pin. LVCMOS/LVTTL interface levels. See Table 3D.
Frequency select pins for QBx outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
Frequency select pins for QC output. See Table 3C.
LVCMOS/LVTTL interface levels.
Frequency select pins for QAx/nQAx outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
Output enable pin for Bank A outputs. See Table 3F. LVCMOS/LVTTL inter-
face levels.
Differential Bank A clock outputs. HCSL interface levels.
External fixed precision resistor (475Ω) from this pin to ground provides a
reference current used for differential current-mode QAx/nQAx clock outputs.
Analog supply pin.
Pullup
Output enable pin for Bank B and Bank C outputs.
LVCMOS/LVTTL Interface levels. See Table 3G.
Single-ended Bank C clock output. LVCMOS/LVTTL interface levels.
18Ω typical output impedance.
Output supply pin for QC LVCMOS output.
Output supply pins for QBx LVCMOS outputs.
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
18Ω typical output impedance.
13
16,
17
18,
19,
20
21,
22,
23
24,
25
26
30, 31
32, 33
34
37, 38
39
41
42
43, 48, 52, 56
44, 45,
47, 49,
51, 53, 55
nMR
SSC1,
SSC0
F_SELB2, F_
SELB1,
F_SELB0
F_SELC2, F_
SELC1,
F_SELC0
F_SELA1, F_
SELA0
QA_OE
nQA1, QA1
nQA0, QA0
IREF
V
DDA
QBC_OE
QC
V
DDOC
V
DDOB
Input
Input
Input
Input
Input
Input
Output
Output
Power
Input
Output
Power
Power
Pulldown
Pulldown
Pullup
QB0, QB1, QB2,
QB3, QB4, QB5, Output
QB6
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc
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January 4, 2016
841S012DI Datasheet
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
QB[0:6], QC
REF_OUT[1:0]
QB[0:6], QC
V
DD
, V
DD_REFOUT
, V
DDOB,
V
DDOC
= 3.465V
Test Conditions
Minimum
Typical
4
19
51
51
18
23
Maximum
Units
pF
pF
kΩ
kΩ
Ω
Ω
T
ABLE
3A. F_SELA F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Inputs
F_SELA1
L
L
H
H
F_SELA0
L
H
L
H
M Divider Value
80
80
80
80
NA Divider Value
20
16
10
8
Output Frequency (25MHz Ref.)
QA[0:1]/nQA[0:1] (MHz)
100 (default)
125
200
250
T
ABLE
3B. F_SELB F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Inputs
F_SELB2
L
L
L
L
H
H
H
H
F_SELB1
L
L
H
H
L
L
H
H
F_SELB0
L
H
L
H
L
H
L
H
M Divider Value
80
80
80
80
80
80
80
80
NB Divider Value
60
40
30
20
16
15
12
10
Output Frequency (25MHz Ref.)
QB[0:6] (MHz)
33.33 (default)
50
66.67
100
125
133.33
166.67
200
T
ABLE
3C. F_SELC F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Inputs
F_SELC2
L
L
L
L
H
H
H
H
F_SELC1
L
L
H
H
L
L
H
H
F_SELC0
L
H
L
H
L
H
L
H
M Divider Value
80
80
80
80
80
80
80
80
NC Divider Value
60
40
30
20
16
15
12
10
Output Frequency (25MHz Ref.)
QC (MHz)
33.33 (default)
50
66.67
100
125
133.33
166.67
200
©2016 Integrated Device Technology, Inc
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January 4, 2016
841S012DI Datasheet
T
ABLE
3D. SSC F
UNCTION
T
ABLE
Input
SSC1
0
0
1
1
SSC0
0
1
0
1
Mode
0 to -0.5% Down-spread
±0.25% Center-spread
±0.25% Center-spread
SSC Off (default)
T
ABLE
3E. REF_SEL F
UNCTION
T
ABLE
Input
REF_SEL
0
1
Input Reference
XTAL
REF_IN
T
ABLE
3F. QA_OE F
UNCTION
T
ABLE
Input
QA_OE
0
1(default)
Function
QA[0:1]/nQA[0:1] disabled (High-Impedance)
QA[0:1]/nQA[0:1] enabled
T
ABLE
3G. QBC_OE F
UNCTION
T
ABLE
Input
QBC_OE
0
Function
QB[0:6] and QC disabled (High-Impedance)
1 (default) QB[0:6] and QC enabled
T
ABLE
3H. REF_OE F
UNCTION
T
ABLE
Input
REF_OE
1
Function
REF_OUT[0:1] enabled
T
ABLE
3I. nMR F
UNCTION
T
ABLE
Input
nMR
0
Function
Device reset, output divider disabled
(High-Impedance)
0 (default) REF_OUT[0:1] disabled (High-Impedance
1 (default) Output enabled
NOTE: This device requires a reset signal after power-up to
function properly.
T
ABLE
3J. BYPASS F
UNCTION
T
ABLE
Input
BYPASS
1
Function
Bypass (reference ÷N)
0 (default) PLL
©2016 Integrated Device Technology, Inc
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January 4, 2016
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