FEMTOCLOCK
®
NG
Crystal-to-LVDS/HCSL Clock Synthesizer
ICS841N254I
DATA SHEET
General Description
The ICS841N254I is a 4-output clock synthesizer designed for S-RIO
1.3 and 2.0 reference clock applications. The device generates four
copies of a selectable 250MHz, 156.25MHz, 125MHz or 100MHz
clock signal with excellent phase jitter performance. The four outputs
are organized in two banks of two LVDS and two HCSL ouputs.The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. The synthesized clock frequency and
the phase-noise performance are optimized for driving RIO 1.3 and
2.0 SerDes reference clocks. The device supports 3.3V and 2.5V
voltage supplies and is packaged in a small 32-lead VFQFN
package. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements.
Features
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Fourth generation FemtoClock® (NG) technology
Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output
clock synthesized from a 25MHz fundamental mode crystal
Four differential clock outputs (two LVDS and two HCSL outputs)
Crystal interface designed for 25MHz,
parallel resonant crystal
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1MHz - 20MHz): 0.27ps (typical)
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.32ps (typical)
Power supply noise rejection PSNR: -50dB (typical)
LVCMOS interface levels for the frequency select input
Full 3.3V or 2.5V supply voltage
Available in both standard (RoHS 5) and Lead-free (RoHS 6)
packages
-40°C to 85°C ambient operating temperature
V
DDOB
nQB0
nQB1
F_SEL0
GND
GND
Function Table
Output Frequency with
f
XTAL
= 25MHz
156.25MHz
125MHz
100MHz
250MHz
QB0
QB1
V
DD
Inputs
F_SEL1
0 (default)
0
1
1
F_SEL0
0 (default)
1
0
1
Pin Assignment
V
DD
nc
1
2
32 31 30 29 28 27 26 25
24 IREF
ICS841N254I
32-lead VFQFN
K Package
5mm x 5mm x 0.925mm
package body
Top View
23 GND
22 nQA0
21 QA0
20 V
DDOA
19 nQA1
18 QA1
17 GND
V
DDA
3
nc 4
GND
REF_CLK
5
6
NOTE: F_SEL[1:0] are asynchronous controls.
nOEA 7
V
DD
8
9
nOEB
10 11 12 13 14 15 16
BYPASS
REF_SEL
XTAL_OUT
XTAL_IN
F_SEL1
V
DD
Block Diagram
XTAL_IN
OSC
XTAL_OUT
REF_CLK
REF_SEL
BYPASS
F_SEL[0:1]
nOEA
nOEB
IREF
Pulldown
1
0
1
PFD
&
LPF
FemtoClock® NG
VCO
625MHz
÷25
÷N
0
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
LVDS
LVDS
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
2
HCSL
HCSL
ICS841N254AKI REVISION A APRIL 18, 2011
1
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 8, 13, 32
2, 4
3
5, 17,
23, 25, 31
6
7
9
10
11,
12
14
15,
16
18, 19
20
21, 22
24
26, 27
28
29, 30
Name
V
DD
nc
V
DDA
GND
REF_CLK
nOEA
nOEB
REF_SEL
XTAL_IN,
XTAL_OUT
BYPASS
F_SEL0,
F_SEL1
QA1, nQA1
V
DDOA
QA0, nQA0
IREF
nQB1, QB1
V
DDOB
nQB0, QB0
Power
Unused
Power
Power
Input
Input
Input
Input
Input
Input
Input
Output
Power
Output
Input
Output
Power
Output
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Type
Description
Core supply pins.
No connect.
Analog power supply.
Power supply ground.
Alternative single-ended reference clock input. LVCMOS/LVTTL interface levels.
Output enable input. See Table 3D for function. LVCMOS/LVTTL interface levels.
Output enable input. See Table 3E for function. LVCMOS/LVTTL interface levels.
Reference select input. See Table 3B for function.
LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Bypass mode select pin. See Table 3C for function.
LVCMOS/LVTTL interface levels.
Frequency select pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
Differential clock output. LVDS interface levels.
Output supply pin for QAx outputs.
Differential clock output. LVDS interface levels.
External fixed precision resistor (475Ω) from this pin to ground provides a reference
current used for differential current-mode QBx, nQBx clock outputs.
Differential clock output. HCSL interface levels.
Output supply pin for QBx outputs.
Differential clock output. HCSL interface levels.
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Ω
ICS841N254AKI REVISION A APRIL 18, 2011
2
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Function Tables
Table 3A. Output Divider and Output Frequency
Inputs
F_SEL1
0 (default)
0
1
1
F_SEL0
0 (default)
1
0
1
Operation
f
OUT
= f
REF
* 25 ÷ 4
f
OUT
= f
REF
* 5
f
OUT
= f
REF
* 4
f
OUT
= f
REF
* 10
f
OUT
with f
REF
= 25MHz
156.25MHz
125MHz
100MHz
250MHz
NOTE: F_SEL[1:0] are asynchronous controls.
Table 3B. PLL Reference Clock Select Function Table
Input
REF_SEL
0 (default)
1
Operation
The crystal interface is selected as reference clock
The REF_CLK input is selected as reference clock
NOTE: REF_SEL is an asynchronous control.
Table 3C. PLL BYPASS Function Table
Input
BYPASS
0 (default)
1
Operation
PLL is enabled. The reference frequency f
REF
is multiplied by the PLL
feedback divider of 25 and then divided by the selected output divider N.
PLL is bypassed. The reference frequency f
REF
is divided by the selected
output divider N. AC specifications do not apply in PLL bypass mode.
NOTE: BYPASS is an asynchronous control.
Table 3D. nOEA Output Enable Function Table
Input
nOEA
0 (default)
1
Operation
QA0, nQA0 and QA1, nQA1 outputs are enabled
QA0, nQA0 and QA1, nQA1 outputs are disabled (high-impedance)
NOTE: nOEA is an asynchronous control.
Table 3E. nOEB Output Enable Function Table
Input
nOEB
0 (default)
1
Operation
QB0, nQB0 and QB1, nQB1 outputs are enabled
QB0, nQB0 and QB1, nQB1 outputs are disabled (high-impedance)
NOTE: nOEB is an asynchronous control.
ICS841N254AKI REVISION A APRIL 18, 2011
3
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
(HCSL)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
3.6V
0V to 2V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
10mA
15mA
37.7°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= V
DDOA
= V
DDOB
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
Parameter
Core Supply Voltage
2.375
Analog Supply Voltage
V
DD
– 0.30
V
DD
– 0.30
3.135
V
DDOA&B
I
DDA
I
DD
I
DDOA&B
Output Supply Voltage
2.375
Analog Supply Current
Power Supply Current
Output Supply Current
2.5
2.625
30
113
72
V
mA
mA
mA
2.5
3.3
2.5
3.3
2.625
V
DD
V
DD
3.465
V
V
V
V
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
V
DDA
Table 4B. LVCMOS/LVTTL
Input
DC Characteristics, V
DD
= V
DDOA
= V
DDOB
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
nOEA, nOEB,
BYPASS, REF_SEL,
REF_CLK, F_SEL[1:0]
nOEA, nOEB,
BYPASS, REF_SEL,
REF_CLK, F_SEL[1:0]
V
DD
= 3.3V
V
DD
= 2.5V
Input High Current
V
DD
= V
IN
= 2.625V or
3.465V
V
DD
= 2.625V or 3.465V,
V
IN
= 0V
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
V
IL
I
IH
I
IL
Input Low Current
-5
µA
ICS841N254AKI REVISION A APRIL 18, 2011
4
©2011 Integrated Device Technology, Inc.
ICS841N254I Data Sheet
FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER
Table 4C. LVDS 3.3V DC Characteristics, V
DD
= V
DDOA
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.1
Test Conditions
Minimum
200
Typical
Maximum
550
50
1.3
50
Units
mV
mV
V
mV
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Test Conditions
Minimum
Typical
Fundamental
25
80
7
MHz
Maximum
Units
Ω
pF
ICS841N254AKI REVISION A APRIL 18, 2011
5
©2011 Integrated Device Technology, Inc.
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