Low Skew, 1-TO-24 Differential-to
LVCMOS Fanout Buffer
G
ENERAL
D
ESCRIPTION
The 8344 is a low voltage, low skew, 1-to-24 Differential-to-LVCMOS
Fanout Buffer. The 8344 is designed to translate any differential
signal levels to LVCMOS levels. The low impedance LVCMOS
outputs are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased to 48
by utilizing the ability of the outputs to drive two series terminated
lines. Redundant clock applications can make use of the dual clock
input. The dual clock inputs also facilitate board level testing. 8344
is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V
output operating supply modes.
Guaranteed output and part-to-part skew characteristics make the
8344 ideal for those clock distribution applications demanding well
defined performance and repeatability.
8344
DATASHEET
F
EATURES
•
Twenty-four LVCMOS outputs, 7Ω typical output impedance
•
Selectable differential clock input pairs for redundant
clock applications
•
CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 167MHz
•
Translates any differential input signal (LVPECL, LVHSTL,
LVDS) to LVCMOS without external bias networks
•
Translates any single-ended input signal to LVCMOS
with resistor bias on nCLK input
•
Multiple output enable pins for disabling unused outputs
in reduced fanout applications
•
Output skew: 275ps (maximum)
•
Part-to-part skew: 600ps (maximum)
•
Bank skew: 150ps (maximum)
•
Propagation Delay: 4.3ns (maximum)
•
3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
•
0°C to 70°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8344 REVISION A 3/24/15
1
©2015 Integrated Device Technology, Inc.
8344 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 5, 6
7, 8, 11, 12
3, 9, 28,
34, 39, 45
4, 10, 14,18,
27, 33, 40, 46
13
15, 19
16
17
20
21
22
23
24
25, 26, 29, 30
31, 32, 35, 36
37, 38, 41, 42
43, 44, 47, 48
Name
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
V
DDO
GND
CLK_SEL
V
DD
nCLK1
CLK1
nCLK0
CLK0
OE3
OE2
OE1
Q0, Q1, Q2, Q3
Q4, Q5, Q6, Q7
Q8, Q9, Q10, Q11
Q12, Q13, Q14, Q15
Type
Output
Power
Power
Input
Power
Input
Input
Input
Input
Input
Input
Input
Output
Output
Pullup
Pullup
Description
Q15 thru Q23 outputs. 7
Ω
typical output impedance.
Output supply pins. Connect 3.3V or 2.5V.
Power supply ground. Connect to ground.
Pulldown
When LOW, selects CLK0, nCLK0 inputs.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs.
Positive supply pins. Connect 3.3V or 2.5V.
Inverting input of secondary differential clock input pair.
Pulldown
Non-inverting input of secondary differential clock input pair.
Inverting input of primary differential clock input pair.
Pulldown
Non-inverting input of primary differential clock input pair.
Pullup
Pullup
Pullup
Output enable. Controls enabling and disabling of outputs
Q16 thru Q23.
Output enable. Controls enabling and disabling of outputs
Q8 thru Q15.
Output enable. Controls enabling and disabling of outputs
Q0 thru Q7.
Q0 thru Q7 outputs. 7
Ω
typical output impedance.
Q8 thru Q15 outputs. 7
Ω
typical output impedance.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
, V
DDO
= 3.465V
V
DD
= 3.465V, V
DDO
= 2.625V
V
DD
, V
DDO
= 2.625V
51
51
7
Test Conditions
Minimum
Typical
Maximum
4
Units
pF
pF
pF
pF
kΩ
kΩ
Ω
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
2
REVISION A 3/24/15
ICS8344 DATA SHEET
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Bank 1
Input
OE1
0
1
Output
Q0-Q7
Hi-Z
Active
Bank 2
Input
OE2
0
1
Output
Q8-Q15
Hi-Z
Active
OE3
0
1
Bank 3
Input
Output
Q16-Q23
Hi-Z
Active
T
ABLE
3B. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
Control Input
CLK_SEL
0
1
Selected
De-selected
Clock
CLK0, nCLK0
CLK1, nCLK1
De-selected
Selected
T
ABLE
3C. C
LOCK
I
NPUTS
F
UNCTION
T
ABLE
Inputs
OE1, OE2, OE3
1
1
1
1
1
1
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
Q0 thru Q23
LOW
HIGH
LOW
HIGH
HIGH
LOW
Input to Output Mode
Differential to Single Ended
Differential to Single Ended
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
REVISION A 3/24/15
3
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
8344 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC
Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Positive Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
120
Units
V
V
mA
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
CLK_SEL,
OE1, OE2, OE3
CLK_SEL,
OE1, OE2, OE3
OE1, OE2, OE3
CLK_SEL
OE1, OE2, OE3
CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465, V
IN
= 0V
V
DD
= 3.465, V
IN
= 0
V
DD
= V
DDO
= 3.135V
I
OH
= -36mA
V
DD
= V
DDO
= 3.135V
I
OL
= 36mA
-150
-5
2.6
0.6
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
-150
-5
0.15
GND + 0.5
1.3
V
DD
- 0.85
Test Conditions
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; Note 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is V
DD
+ 0.3V.
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
4
REVISION A 3/24/15
ICS8344 DATA SHEET
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
tp
LH
tp
HL
tsk(b)
tsk(o)
tsk(pp)
t
R
t
F
t
PW
t
EN
t
DIS
Parameter
Output Frequency
Propagation Delay
Low-to-High; NOTE 1
Propagation Delay
High-to-Low; NOTE 1
Bank Skew; NOTE 2, 6
Output Skew; NOTE 3, 6
Part-to-Part Skew; NOTE 4, 6
Output Rise Time; NOTE 5
Output Fall Time; NOTE 5
Output Pulse Width
Output Enable Time; NOTE 5
Output Disable TIme; NOTE 5
f
≤
167MHz
f
≤
167MHz
Measured on the
rising edge of V
DDO
/2
Measured on the
rising edge of V
DDO
/2
Measured on the
rising edge of V
DDO
/2
30% to 70%
30% to 70%
f
≤
167MHz
f = 167MHz
f = 66.7MHz
f = 66.7MHz
200
200
tPeriod/2 - 0.65
2.35
tPeriod/2
2.5
2.6
2.4
Test Conditions
Minimum
Typical
Maximum
167
4.3
4.3
150
275
600
1000
1000
tPeriod/2 + 0.65
3.65
5
4
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ns
ns
ns
ns
All parameters measured at 167MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
REVISION A 3/24/15
5
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PCB设计
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