Low Skew, 1-to-24
Differential-to-LVCMOS/LVTTL Fanout Buffer
General Description
The ICS8344I-01 is a low voltage, low skew fanout buffer. The
ICS8344I-01 has two selectable clock inputs. The CLKx, nCLKx
pairs can accept most standard differential input levels. The
ICS8344I-01 is designed to translate any differential signal level to
LVCMOS/LVTTL levels. The low impedance LVCMOS/LVTTL
outputs are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased to 48 by
utilizing the ability of the outputs to drive two series terminated lines.
Redundant clock applications can make use of the dual clock inputs
which also facilitate board level testing. The clock enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin. The
outputs are driven low when disabled. The ICS8344I-01 is
characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V
output operating supply modes.
Guaranteed output and part-to-part skew characteristics make the
ICS8344I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
ICS8344I-01
DATA SHEET
Features
•
•
•
•
•
•
•
•
•
•
•
•
Twenty-four LVCMOS/LVTTL outputs,
7Ω typical output impedance
Two selectable differential CLKx, nCLKx inputs
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following
input levels: LVDS, LVPECL, LVHSTL, HCSL
Maximum output frequency: 100MHz
Translates any single ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
Synchronous clock enable
Additive phase jitter, RMS: 0.21ps (typical)
Output skew: 200ps (maximum)
Part-to-part skew: 900ps (maximum)
Bank skew: 180ps (maximum)
Propagation delay: 5ns (maximum)
Output supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
-40°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
•
•
Block Diagram
CLK_SEL
Pulldown
CLK0
Pulldown
nCLK0
Pullup
CLK1
Pulldown
nCLK1
Pullup
Pin Assignment
Q15
Q14
GND
V
DDO
Q13
Q12
Q11
Q10
GND
V
DDO
Q9
Q8
0
1
8
Q[0:7]
8
Q[8:15]
Q16
Q17
V
DDO
GND
Q18
Q19
Q20
Q21
V
DDO
GND
Q22
Q23
8
Q[16:23]
LE
CLK_EN
Pullup
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
5
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
CLK_SEL
GND
V
DD
nCLK1
CLK1
GND
V
DD
nCLK0
CLK0
CLK_EN
OE
nc
Q7
Q6
V
DDO
GND
Q5
Q4
Q3
Q2
V
DDO
GND
Q1
Q0
Q
nD
OE
Pullup
ICS8344I-01
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8344AYI-01 REVISION A FEBRUARY 29, 2012
1
©2012 Integrated Device Technology, Inc.
ICS8344I-01 Data Sheet
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2, 5, 6,
7, 8, 11, 12
3, 9, 28,
34, 39, 45
4, 10,
14, 18, 27,
33, 40, 46
13
15, 19
16
17
20
21
22
23
24
25, 26, 29, 30,
31, 32, 35, 36
37, 38, 41, 42,
43, 44, 47, 48
Name
Q16, Q17, Q18,
Q19, Q20, Q21,
Q22, Q23
V
DDO
GND
Output
Type
Description
Single-ended clock outputs. 7
Ω
typical output Impedance.
LVCMOS/LVTTL interface levels.
Output supply pins.
Power
Power
Power supply ground.
Clock select input. When HIGH, selects CLK1, nCLK inputs, When LOW,
selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
Power supply pins.
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pullup
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Synchronizing control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q[0:23].
LVCMOS / LVTTL interface levels.
No connect.
Single-ended clock outputs. 7
Ω
typical output Impedance.
LVCMOS/LVTTL interface levels.
Single-ended clock outputs. 7
Ω
typical output Impedance.
LVCMOS/LVTTL interface levels.
CLK_SEL
V
DD
nCLK1
CLK1
nCLK0
CLK0
CLK_EN
OE
nc
Q0, Q1, Q2, Q3,
Q4, Q5, Q6, Q7
Q8, Q9, Q10,
Q11, Q12, Q13,
Q14, Q15
Input
Power
Input
Input
Input
Input
Input
Input
Unused
Output
Pulldown
Output
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DDO
= 3.3V±5% or 2.5V±5%
V
DD
= V
DDO
= 3.465V
V
DD
= V
DDO
= 2.625V
Test Conditions
Minimum
Typical
4
23
16
51
51
7
Maximum
Units
pF
pF
pF
k
Ω
k
Ω
Ω
ICS8344AYI-01 REVISION A FEBRUARY 29, 2012
2
©2012 Integrated Device Technology, Inc.
ICS8344I-01 Data Sheet
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Function Tables
Table 3A. Output Enable Function Table
Control Input
OE
0
1
1
CLK_EN
X
0
1
Outputs
Q[0:23]
High-Impedance
Disabled in Logic LOW state; NOTE 1
Enabled; NOTE 1
NOTE 1: The clock enable and disable function is synchronous to the falling edge of the selected reference clock.
Table 3A. Clock Select Function Table
Control Input
CLK_SEL
0
1
CLK0, nCLK0
Selected
De-selected
Clock
CLK1, nCLK1
De-selected
Selected
Table 3C. Clock Input Function Table
Inputs
OE
1 (default)
1
1
1
1
1
CLK0, CLK1
0 (default)
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK0, nCLK1
1 (default)
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
Q[0:23]
LOW
HIGH
LOW
HIGH
HIGH
LOW
Input to Output Mode
Differential to Single-Ended
Differential to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information Section,
Wiring the Differential Input to Accept Single-ended Levels.
ICS8344AYI-01 REVISION A FEBRUARY 29, 2012
3
©2012 Integrated Device Technology, Inc.
ICS8344I-01 Data Sheet
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
53.9°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, or V
DD
= V
DDO
= 2.5V ± 5%, or
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 70°C
Symbol
V
DD
Parameter
Power Supply Voltage
2.375
3.135
V
DDO
I
DD
Output Supply Voltage
2.375
Power Supply Current
2.5
2.625
95
V
mA
2.5
3.3
2.625
3.465
V
V
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
Table 4B. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
Input Low Voltage
Input
High Current
Input
Low Current
OE, CLK_EN
CLK_SEL
OE, CLK_EN
CLK_SEL
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DDO
= 3.135V, I
OH
= -36mA
V
DDO
= 2.375V, I
OH
= -27mA
Output Low Voltage
V
DDO
= 3.135V, I
OL
= 36mA
V
DDO
= 2.375V, I
OL
= 27mA
-150
-5
2.7
1.9
0.5
0.5
Minimum
2
2
-0.3
-0.3
Typical
Maximum
3.8
2.9
0.8
0.8
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
IL
I
IH
I
IL
V
OH
Output High Voltage
V
OL
ICS8344AYI-01 REVISION A FEBRUARY 29, 2012
4
©2012 Integrated Device Technology, Inc.
ICS8344I-01 Data Sheet
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 4C. Differential DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, or V
DD
= V
DDO
= 2.5V ± 5%, or
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 70°C
Symbol
I
IH
Parameter
Input
High Current
Input
Low Current
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
-5
0.3
0.9
1.3
2.0
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
V
CMR
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, or V
DD
= V
DDO
= 2.5V ± 5%, or
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 70°C
Symbol
f
OUT
t
PD
tjit
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Q[0:7]
tsk(b)
tsk(o)
tsk(pp)
t
R
/ t
F
t
EN
t
DIS
odc
Bank Skew;
NOTE 2, 6
Q[8:15]
Q[16:23]
Output Skew; NOTE 3, 6
Part-to-Part Skew; NOTE 4, 6
Output Rise/Fall Time; NOTE 5
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
Output Duty Cycle
Measured on the rising edge of V
DDO
/2
Measured on the rising edge of V
DDO
/2
30% to 70%
f = 10MHz
f = 10MHz
f
≤
100MHz
45
200
Measured on the rising edge of V
DDO
/2
f
≤
100MHz
100MHz,
Integration Range: 12kHz – 20MHz
2.5
0.21
155
180
140
200
900
800
5
4
55
Test Conditions
Minimum
Typical
Maximum
100
5
Units
MHz
ns
ps
ps
ps
ps
ps
ps
ps
ns
ns
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at
≤100MHz
and V
PP_
typ unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to V
DDO
/2.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as between outputs at the same supply voltages and with equal load conditions. Measured at V
DDO
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
ICS8344AYI-01 REVISION A FEBRUARY 29, 2012
5
©2012 Integrated Device Technology, Inc.
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