LOW SKEW, 1-TO-24 DIFFERENTIAL-
TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8344-01
G
ENERAL
D
ESCRIPTION
The ICS8344-01 is a low voltage, low skew
fanout buffer and a member of the HiPerClockS ™
HiPerClockS™
family of High Performance Clock Solutions from
IDT. The ICS8344-01 has two selectable clock in-
puts. The CLKx, nCLKx pairs can accept most
standard differential input levels. The ICS8344-01 is designed
to translate any differential signal level to LVCMOS/LVTTL lev-
els. The low impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmission lines.
The effective fanout can be increased to 48 by utilizing the
ability of the outputs to drive two series terminated lines.
Redundant clock applications can make use of the dual clock
inputs which also facilitate board level testing. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin. The outputs are driven low when disabled.
The ICS8344-01 is characterized at full 3.3V, full 2.5V and mixed
3.3V input and 2.5V output operating supply modes.
F
EATURES
•
Twenty-four LVCMOS/LVTTL outputs,
7Ω typical output impedance
•
Two selectable differential CLKx, nCLKx inputs
•
CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Output frequency up to 250MHz
•
Translates any single ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
•
Synchronous clock enable
•
Additive phase jitter RMS: 0.21ps (typical)
•
Output skew: 200ps (maximum)
•
Part-to-part skew: 900ps (maximum)
•
Bank skew: 85ps (maximum)
•
Propagation delay: 5ns (maximum)
•
Output supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
Guaranteed output and part-to-part skew characteristics make
the ICS8344-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_SEL
Pulldown
CLK0
Pulldown
nCLK0
Pullup
CLK1
Pulldown
nCLK1
Pullup
0
1
Q0:Q7
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
48-Lead LQFP
6
31
7mm x 7mm x 1.4mm
7
30
package body
8
29
Y Package
9
28
Top View
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
Q8
Q9
V
DDO
GND
Q10
Q11
Q12
Q13
V
DDO
GND
Q14
Q15
Q8:Q15
Q16:Q23
LE
Q
Q16
Q17
V
DDO
GND
Q18
Q19
Q20
Q21
V
DDO
GND
Q22
Q23
ICS8344-01
Q7
Q6
V
DDO
GND
Q5
Q4
Q3
Q2
V
DDO
GND
Q1
Q0
CLK_EN
Pullup
nc
OE
CLK_EN
CLK0
nCLK0
V
DD
GND
CLK1
nCLK1
V
DD
GND
CLK_SEL
nD
OE
Pullup
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER
1
ICS8344AY-01 REV. C SEPTEMBER 9, 2008
ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 5, 6
7, 8, 11, 12
3, 9, 28,
34, 39, 45
4, 10, 14,18,
27, 33, 40, 46
13
15, 19
16
17
20
21
22
23
Name
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
V
DDO
GND
CLK_SEL
V
DD
nCLK1
CLK1
nCLK0
CLK0
CLK_EN
OE
Type
Output
Power
Power
Input
Power
Input
Input
Input
Input
Input
Input
Description
Q16 thru Q23 outputs. 7
Ω
typical output impedance.
Output supply pins. Connect 3.3V or 2.5V.
Power supply ground. Connect to ground.
Clock select input. When HIGH, selects CLK1, nCLK inputs,
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levelss.
Positive supply pins. Connect 3.3V or 2.5V.
Pullup
Pullup
Inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
Pulldown Non-inver ting differential LVPECL clock input.
Pulldown Non-inver ting differential LVPECL clock input.
Synchronizing control for enabling and disabling clock outputs.
Pullup
LVCMOS interface levels.
Output enable. Controls enabling and disabling of outputs
Pullup
Q0 thru Q23.
No connect.
24
nc
Unused
25, 26, 29, 30
Q0, Q1, Q2, Q3
Output
Q0 thru Q7 outputs. 7
Ω
typical output impedance.
31, 32, 35, 36
Q4, Q5, Q6, Q7
37, 38, 41, 42
Q8, Q9, Q10, Q11
Output
Q8 thru Q15 outputs. 7
Ω
typical output impedance.
43, 44, 47, 48 Q12, Q13, Q14, Q15
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
Parameter
Input Capacitance
CLK0, nCLK0,
CLK1, nCLK1
CLK_SEL,
CLK_EN, OE
V
DDO
= 3.465V
V
DDO
= 2.675V
23
16
51
51
7
Test Conditions
Minimum
Typical
Maximum
4
4
Units
pF
pF
pF
pF
kΩ
kΩ
Ω
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER
2
ICS8344AY-01 REV. C SEPTEMBER 9, 2008
ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Banks 1, 2, 3
Inputs
OE
0
1
CLK_EN
X
0
Outputs
Q0-Q23
Hi-Z
Disabled in logic LOW state. NOTE 1
1 (default)
1 (default)
Enabled. NOTE 1
NOTE 1: The clock enable and disable function is synchronous to the falling
edge of the selected reference clock.
T
ABLE
3B. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
Control Input
CLK_SEL
0 (default)
1
CLK0, nCLK0
Selected
De-selected
Clock
CLK1, nCLK1
De-selected
Selected
T
ABLE
3C. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
OE
1 (default)
1
1
1
1
CLK0, CLK1
0 (default)
1
0
1
Biased; NOTE 1
nCLK0, nCLK1
1 (default)
0
Biased; NOTE 1
Biased; NOTE 1
0
Outputs
Q0 thru Q23
LOW
HIGH
LOW
HIGH
HIGH
Input to Output Mode
Differential to Single Ended
Differential to Single Ended
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
1
Biased; NOTE 1
1
LOW
Single Ended to Differential
Inver ting
NOTE 1: Please refer to the Application Information section on page 8, Figure 1, which discusses
Wiring the Differential
Input to Accept Single-Ended Levels.
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER
3
ICS8344AY-01 REV. C SEPTEMBER 9, 2008
ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Quiescent Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
95
Units
V
V
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Quiescent Power Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
95
Units
V
V
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Quiescent Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
95
Units
V
V
mA
T
ABLE
4D. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
CLK_SEL, CLK_EN,
OE
CLK_SEL, CLK_EN,
OE
CLK_EN, OE
CLK_SEL
CLK_EN, OE
CLK_SEL
Test Conditions
Minimum
2
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465, V
IN
= 0V
V
DD
= 3.465, V
IN
= 0V
V
DD
= V
DDO
= 3.135V
I
OH
= -36mA
V
DD
= V
DDO
= 3.135V
I
OL
= 36mA
-150
-5
2.7
0.5
Typical
Maximum
3.8
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER
4
ICS8344AY-01 REV. C SEPTEMBER 9, 2008
ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
T
ABLE
4E. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_SEL, CLK_EN,
OE
CLK_SEL, CLK_EN,
OE
CLK_EN, OE
CLK_SEL
CLK_EN, OE
CLK_SEL
Test Conditions
Minimum
2
-0.3
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465, V
IN
= 0V
V
DD
= 3.465, V
IN
= 0V
V
DD
= 3.135V
V
DDO
= 2.375V
I
OH
= -27mA
V
DD
= 3.135V
V
DDO
= 2.375V
I
OL
= 27mA
-150
-5
1.9
Typical
Maximum
3.8
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
Output High Voltage
V
OL
Output Low Voltage
0.4
V
T
ABLE
4F. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
CLK_SEL, CLK_EN,
OE
CLK_SEL, CLK_EN,
OE
CLK_EN, OE
CLK_SEL
CLK_EN, OE
CLK_SEL
Test Conditions
Minimum
2
-0.3
V
DD
= V
IN
= 2.625V
V
DD
= V
IN
= 2.625V
V
DD
= 2.625, V
IN
= 0V
V
DD
= 2.625, V
IN
=0V
V
DD
= V
DDO
= 2.375V
I
OH
= -27mA
V
DD
= V
DDO
= 2.375V
I
OL
= 27mA
-150
-5
1.9
0.4
Typical
Maximum
2.9
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER
5
ICS8344AY-01 REV. C SEPTEMBER 9, 2008
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