Features
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Eight General-purpose Floating-point Data Registers, Each Supporting a Full 80-bit
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Extended Precision Real Data Format (a 64-bit Mantissa Plus a Sign Bit, and a 15-bit
Signed Exponent)
A 67-bit Arithmetic Unit to Allow Very Fast Calculations with Intermediate are Precision
Greater than the Extended Precision Format
A 67-bit Barrel Shifter for High-speed Shifting Operations (for Normalizing etc.)
Special-purpose Hardware for High-speed Conversion Between Single, Double, and
Extended Formats and the Internal Extended Format
An Independent State Machine to Control Main Processor Communication for
Pipelined Instruction Processing
Forty-six Instructions, Including 35 Arithmetic Operations
Full Conformation to the IEEE 754 Standard, Including All Requirements and
Suggestions
Support of Functions Not Defined by the IEEE Standard, Including a Full Set of
Trigonometric and Transcendental Functions
Seven Data Type Types: Byte, Word and Long Integers; Single, Double, and Extended
Precision Real Numbers; and Packed Binary Coded Decimal String Real Numbers
Twenty-two Constants Available In The On-chip ROM, Including
π,
e, and Powers of 10
Virtual Memory/Machine Operations
Efficient Mechanisms for Procedure Calls, Context Switches, and Interrupt Handling
Fully Concurrent Instruction Execution with the Main Processor
Fully Concurrent Instruction Execution of Multiple Floating-point Instructions
Use with any Host Processor, on an 8-, 16- or 32-bit Data Bus
Available in 16.67, 20, 25 and 33 MHz for T
c
from -55°C to +125°C
V
CC
= 5V
±
10%
CMOS
Enhanced
Floating-point
Co-processor
TS68882
Description
The TS68882 enhanced floating-point co-processor is a full implementation of the
IEEE Standard for Binary Floating-Point Arithmetic (754) for use with the THOMSON
TS68000 Family of microprocessors. It is a pin and software compatible upgrade of
the TS68881 with optimized MPU interface that provides over 1.5 times the perfor-
mance of the TS68881. It is implemented using VLSI technology to give systems
designers the highest possible functionality in a physically small device.
Intended primarily for use as a co-processor to the TS68020/68030 32-bit micropro-
cessor units (MPUs), the TS68882 provides a logical extension to the main MPU
integer data processing capabilities. It does this by providing a very high performance
floating-point arithmetic unit and a set of floating-point data registers that are utilized
in a manner that is analogous to the use of the integer data registers. The TS68882
instruction set is a natural extension of all earlier members of the TS68000 Family, and
supports all of the addressing modes of the host MPU. Due to the flexible bus inter-
face of the TS68000 Family, the TS68882 can be used with any of the MPU devices of
the TS68000 Family, and it may also be used as a peripheral to non-TS68000
processors.
Screening/Quality
This product could be manufactured
in full compliance with either:
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MIL-STD-883 Class B
DESC 5962-89436
or According to ATMEL-
Grenoble Standards
Rev. 2119A–HIREL–04/02
R suffix
PGA 68
Ceramic Pin Grid Array
F suffix
CQFP 68
Ceramic Quad Flat Pack
1
Introduction
The TS68882 is a high-performance floating-point device designed to interface with the
TS68020 or TS68030 as a co-processor. This device fully supports the TS68000 virtual
machine architecture, and is implemented in HCMOS, Atmel’s low power, small geome-
try process. This process allows CMOS and HMOS (high-density NMOS) gates to be
combined on the same device. CMOS structures are used where speed and low power
is required, and HMOS structures are used where minimum silicon area is desired. The
HCMOS technology enables the TS68882 to be very fast while consuming less power
than comparable HMOS, and still have a reasonably small die size.
With some performance degradation, the TS68882 can also be used as a peripheral
processor in systems where the TS68020 or TS68030 is not the main processor (i.e.,
TS68000, TS68010). The configuration of the TS68882 as a peripheral processor or co-
processor may be completely transparent to user software (i.e., the same object code
may be executed in either configuration).
The architecture of the TS68882 appears to the user as a logical extension of the
TS68000 Family architecture. Coupling of the co-processor interface allows the
TS68020/TS68030 programmer to view the TS68882 registers as though the registers
are resident in the TS68020/TS68030. Thus, a TS68020 or TS68030/TS68882 device
pair appears to be one processor that supports seven floating-point and integer data
types, and has eight integer data registers, eight address registers, and eight floating-
point data registers.
As shown in Figure 1, the TS68882 is internally divided into four processing elements;
the Bus Interface Unit (BIU), the Conversion Control Unit (CCU), the Execution Control
Unit (ECU), and the Microcode Control Unit (MCU). The BIU communicates with the
main processor, the CCU controls the main processor communications dialog and per-
forms some data conversions, and the ECU and MCU execute most floating-point
calculations.
The BIU contains the co-processor interface registers, and the 32-bit control, and
instruction address registers. In addition to these registers, the register select and
DSACK timing control logic is contained in the BIU. Finally, the status flags used to mon-
itor the status of communications with the main processor are contained in the BIU.
The CCU contains special-purpose hardware that performs conversions between the
single, double, and extended precision memory data formula and the internal data for-
mat used by the ECU. It also contains a state machine that controls communications
with the main processor during co-processor interface dialogs.
The eight 80-bit floating-point data registers (FP0-FP7) are located in the ECU. In addi-
tion to these registers, the ECU contains a high-speed 67-bit arithmetic unit used for
both mantissa and exponent calculations, a barrel shifter that can shift from 1-bit to 67-
bits in one machine cycle, and ROM constants (for use by the internal algorithms or user
programs).
The MCU contains the clock generator, a two-level microcoded sequencer that controls
the ECU, the microcode ROM, and self-test circuitry. The built-in self-test capabilities of
the TS68882 enhance reliability and ease manufacturing requirements; however, these
diagnostic functions are not available to the user.
2
TS68882
2119A–HIREL–04/02
TS68882
Figure 1.
TS68882 Simplified Block
3
2119A–HIREL–04/02
Pin Assignments
Figure 2.
PGA Terminal Designation
* Reserved for future ATMEL-Grenoble use
4
TS68882
2119A–HIREL–04/02
TS68882
Figure 2b.
CQFP Terminal Designation
Functional Signal
Descriptions
This section contains a brief description of the input and output signals for the TS68882
floating-point co-processor. The signals are functionally organized into groups as shown
in Figure 3.
Figure 3.
TS68882 Input/output Signals
Note:
The terms assertion and negation are used extensively. This is done to avoid confusion
when describing “active-low” and “active-high” signals. The term assert or assertion is
used to indicate that a signal is active or true, independent of whether that level is repre-
sented by a high or low voltage. The term negate or negation is used to indicate that a
signal is inactive or false.
5
2119A–HIREL–04/02
NXP MCU
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