Features
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8 Independent Receivers (Rx)
3 Independent Transmitters (Tx)
Full TS68K Family Microprocessor Interface Compatibility
16-bit Data-bus
ARINC 429 Interface: “1” and “0” Lines, RZ Code
Support all ARINC 429 Data Rate Transfer and up to 2.5 Mbit/s
Multi Label Capability
Parity Control: Odd, Even, No Parity, Interrupt Capability
Independent Programmable Frequency for Rx and Tx Channels
8 Messages FIFO per Tx Channel
Independent Interrupt Request Line for Rx and Tx Functions
Vectored Interrupts
Daisy Chain Capability
Direct Addressing of all Registers
Test Modes Capability
20 MHz Operating Frequency
Self-test Capability for Receiver Label Memories and Transmit FiFO
Low Power: 400 mW
Description
The TS68C429A is an ARINC 429 controller. It is an enhanced version of the EF 4442
and it is designed to be connected to the new 16- or 32-bit microprocessors, espe-
cially these of the
Atmel
TS68K family.
CMOS
ARINC 429
Multichannel
Receiver/
Transmitter
(MRT)
TS68C429A
Screening
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MIL-STD-883, class B
DESC Drawing 5962-955180
Atmel
Standards
Application Note
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A detailed application note is available “AN 68C429A” on request.
R suffix
PGA 84
Ceramic Pin Grid Array
F suffix
CQFP 132
Ceramic Quad Flat Pack
Rev. 2120A–HIREL–08/02
1
Hardware Overview
The TS68C429A is a high performance ARINC 429 controller designed to interface pri-
mary to the
Atmel
TS68K family microprocessor in a straight forward fashion (see
“Application Notes” on page 33). It can be connected to any TS68K processor family
with an asynchronous bus with some additional logic in some cases.
As shown in Figure 1, the TS68C429A is divided into five main blocks, the microproces-
sor interface unit (MIU), the logical control unit (LCU), the interrupt control unit (ICU), the
receiver channel unit (RCU) and the transmitter channel unit (TCU).
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The MIU handles the interface protocol of the host processor. Through this unit, the
host sees the TS68C429A as a set of registers.
The LCU controls the internal data flow and initializes the TS68C429A.
The ICU manages one interrupt line for the RCU and one for the TCU. Each of
these two parts has a daisy chain capability. All channels have a dedicated vectored
interrupt answer. Receiver channels priority is programmable.
The RCU is composed of 8 ARINC receiver channels made of:
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a serial to parallel converter to translate the two serial signals (the “1” and “0”
in RZ code) into two 16-bit words,
a memory to store the valid labels,
a control logic to check the validity of the received message,
a buffer to keep the last valid received message.
a parallel to serial converter to translate the messages into two serial signals
(the “1” and “0” in RZ code),
a FIFO memory to store eight 32-bit ARINC messages,
a control logic to synchronize the message transmitter (parity, gap, speed,
etc.).
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The TCU is composed of three ARINC transmitter channels made of:
Test facility: Rx inputs can be internally connected to TX3 output.
Self-test facility: The receiver control label matrix and transmitter FIFO can be
tested. This self-test can be used to verify the integrity of the TS68C429A
memories.
2
TS68C429A
2120A–HIREL–08/02
TS68C429A
Figure 1.
Simplified Block Diagram
3
2120A–HIREL–08/02
Package
Figure 1.
Signal Description
Pin Name
A0-8
D0-15
Type
I
I/O
See “Package Mechanical Data” on page 40 and “Terminal Connections” on page 41.
Function
Address bus. The address bus is used to select one of the internal registers during a processor
read or write cycle.
This bi-directional bus is used to receive data from or transmit data to an internal register during a
processor read or write cycle. During an interrupt acknowledge cycle, the vector number is given
on the lower data bus (D0 - D7).
Chip select (active low). This input is used to select the chip for internal register access.
Lower data strobe. This input (active low) validates lower data during R/W access (D0-D7).
Upper data strobe. This input (active low) validates upper data during R/W access (D8-D15).
Read/write. This input defines a data transfer as a read (high) or a write (low) cycle.
Data transfer acknowledge. If the bus cycle is a processor read, the chip asserts DTACK to
indicate that the information on the data bus is valid. If the bus cycle is a processor write, DTACK
acknowledges the acceptance of the data by the MRT. DTACK will be asserted during chip select
access (CS asserted) or interrupt acknowledge cycle (IACKTX or IACKRK asserted).
Interrupt transmit request. This open drain output signals to the processor that an interrupt is
pending from the transmission part of the MRT. There are 6 causes that can generate an
interrupt request (2 per channel: FIFO empty and end of transmission).
Interrupt transmit acknowledge. If IRQTX is active, the MRT will begin an interrupt acknowledge
cycle. The MRT will generate a vector number to the processor which is the highest priority
channel requesting interrupt service.
Interrupt transmit enable in. This input, together with IEOTX signal, provides a daisy chained
interrupt structure for a vectored scheme. IEITX (active low) indicates that no higher priority
device is requesting interrupt service.
Interrupt transmit enable out. This output, together with IEITX signal, provides a daisy chained
interrupt structure for a vectored interrupt scheme. IEOTX (active low) indicates to lower priority
devices that neither the TS68C429A nor any highest priority peripheral is requesting an interrupt.
Interrupt transmit request. This open drain output signals to the processor that an interrupt is
pending from the receiving part of the chip. There are 9 causes that can generate an interrupt
request (1 per channel: valid message received, and 1 for bad parity on a received message).
Interrupt receive acknowledge. Same function as IACKTX but for receiver part.
Interrupt receive enable in. Same function as IEITX but for receiver part.
Interrupt receive enable out. Same function as IEOTX but for receiver part.
Transmission “1” line of the channel 1.
Transmission “0” line of the channel 1.
Transmission “1” line of the channel 2.
Transmission “0” line of the channel 2.
Transmission “1” line of the channel 3.
Transmission “0” line of the channel 3.
Receiving “1” line of the channel 1.
Receiving “0” line of the channel 1.
Receiving “1” line of the channel 2
CS
LDS
UDS
R/W
DTACK
I
I
I
I
O
IRQTX
O
IACKTX
I
IEITX
I
IEOTX
O
IRQRX
O
IACKRX
IEIRX
IEORX
TX1H
TX1L
TX2H
TX2L
TX3H
TX3L
RX1H
RX1L
RX2H
I
I
I
O
O
O
O
O
O
I
I
I
4
TS68C429A
2120A–HIREL–08/02
TS68C429A
Figure 1.
Signal Description (Continued)
Pin Name
RX2L
RX3H
RX3L
RX4H
RX4L
RX5H
RX5L
RX6H
RX6L
RX7H
RX7L
RX8H
RX8L
RESET
V
CC
/GND
CLK-SYS
CLK-ARINC
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Function
Receiving “0” line of the channel 2.
Receiving “1” line of the channel 3.
Receiving “0” line of the channel 3.
Receiving “1” line of the channel 4.
Receiving “0” line of the channel 4.
Receiving “1” line of the channel 5.
Receiving “0” line of the channel 5.
Receiving “1” line of the channel 6.
Receiving “0” line of the channel 6.
Receiving “1” line of the channel 7.
Receiving “0” line of the channel 7.
Receiving “1” line of the channel 8.
Receiving “0” line of the channel 8.
This input (active low) will initialize the TS68C429A registers.
These inputs supply power to the chip. The V
CC
is powered at +5 volts and GND is the ground
connection.
The clock input is a single-phase signal used for internal timing of processor interface.
This input provides the timing clock to synchronize received/transmitted messaged.
5
2120A–HIREL–08/02
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