®
TS68HC901
HCMOS MULTI-FUNCTION PERIPHERAL
The TS68HC901 CMFP (CMOS Multi-Function
Peripheral) is a combination of many of the neces-
sary peripheral functions in a microprocessor sys-
tem.
Included are :
8 INPUT/OUTPUT PINS
•
Individually programmable direction
•
Individual interrupt source capability
-
Programmable edge selection
16 SOURCE INTERRUPT CONTROLLER
•
8 Internal sources
•
8 External sources
•
Individual source enable
•
Individual source masking
•
Programmable interrupt service modes
-
Polling
-
Vector generation
-
Optional In-service status
•
Daisy chaining capability
FOUR TIMERS WITH INDIVIDUALLY
PROGRAMMABLE PRESCALING
•
Two multimode timers
-
Delay mode
-
Pulse width measurement mode
-
Event counter mode
•
Two delay mode timers
•
Independent clock input
•
Time out output option
SINGLE CHANNEL USART
•
Full Duplex
•
Asynchronous to 65 kbps
•
Byte synchronous to 1 Mbps
•
Internal/External baud rate generation
•
DMA handshake signals
•
Modem control
•
Loop back mode
68000 BUS COMPATIBLE
.
.
.
.
.
48
PDIP48
1
PLCC52
(Ordering Information at the end of the Datasheet
DESCRIPTION
The use of the CMFP in a system can significantly
reduce chip count, thereby reducing system cost.
The CMFP is completely 68000 bus compatible, and
24 directly addressable internal registers provide
the necessary control and status interface to the pro-
grammer.
The CMFP is a derivative of the MK3801 STI, a Z80
family peripheral.
1/42
September 1992
TS68HC901
INTRODUCTION
The TS68HC901 multi-function peripheral (CMFP)
is a member of the 68000 peripherals. The CMFP
directly interfaces to the 68000 processor via an a-
synchronous bus structure. Both vectored and pol-
led interrupt schemes are supported, with the CMFP
providing unique vector number generation for each
of its 16 interrupt sources. Additionally, handshake
lines are provided to facilitate DMAC interfacing. Re-
fer to block diagram of the TS68HC901.
The TS68HC901 performs many of the functions
common to most microprocessor-based systems.
The resources available to the user include:
Eight Individually Programmable I/O Pins with In-
terrupt Capability
16-Source Interrupt Controller with Individual
Source Enabling and Masking
Four Timers, Two of which are Multi-Mode Ti-
mers
Figure 1:
TS68HC901 Block Diagram
.
.
.
.
.
Timers may be used as Baud Rate Generators
for the Serial Channel
Single-Channel Full-Duplex Universal Synchro-
nous / Asynchronous Receiver-Transmitter (U-
SART) that Supports Asynchronous and with the
Addition of a Polynomial Generator Checker
Supports Byte Synchronous Formats
By incorporating multiple functions within the CMFP,
the system designer retains flexibility while minimi-
zing device count.
From a programmer’s point of view, the versatility of
the CMFP may be attributed to its register set. The
registers are well organized and allow the CMFP to
be easily tailored to a variety of applications. All of
the 24 registers are also directly addressable which
simplifies programming. The register map is shown
in Figure 2.
2/42
®
TS68HC901
Figure 2 : CMFP Register Map.
Address
Binary
Hex
RS5
01
03
05
07
09
0B
0D
0F
11
13
15
17
19
1B
1D
1F
21
23
25
27
29
2B
2D
2F
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RS4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
RS3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RS2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RS1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GPIP
AER
DDR
IERA
IERB
IPRA
IPRB
ISRA
ISRB
IMRA
IMRB
VR
TACR
TBCR
TCDCR
TADR
TBDR
TCDR
TDDR
SCR
UCR
RSR
TSR
UDR
General Purpose I/O Register
Active Edge Register
Data Direction Register
Interrupt Enable Register A
Interrupt Enable Register B
Interrupt Pending Register A
Interrupt Pending Register B
Interrupt In-service Register A
Interrupt In-service Register B
Interrupt Mask Register A
Interrupt Mask Register B
Vector Register
Timer A Control Register
Timer B Control Register
Timers C and D Control Register
Timer A Data Register
Timer B Data Register
Timer C Data Register
Timer D Data Register
Synchronous Character Register
USART Control Register
Receiver Status Register
Transmitter Status Register
USART Data Register
Abbreviation
Register Name
Note :
Hex addresses assume that RS1 connects with A1, RS 2connects wi th A2, etc.. . and that DS is connected t o LDS on
the 68000 or DS is connect to DS on the 68008.
3/42
®
TS68HC901
Figure 3 : PDIP Pin connection
Figure 4 : PLCC Pin connection
Pin
48
47
1
35
MOTOROLA
6800 Type
CS
E
R/W
V
SS
MOTOROLA
Multiplexed
CS
DS
R/W
AS
INTEL
CS
RD
WR
ALE
PIN DESCRIPTION
GND :
V
CC
:
R/W :
Ground
+5 volts (± 5%)
Read/Write (input). This input defines a
data transfert as a Read (High) or Write
(Low) cycle. This signal is used as WR
with an Intel processor type.
DTACK : This output signals the completion of the
operation phase of a bus cycle to the pro-
cessor. If the bus cycle is a processor
read, the CMFP asserts DTACK to indi-
cate that the information on the Data bus
is valid. If the bus cycle is a processor to
the CMFP, DTACK acknowledges the
acceptance of the data by the CMFP.
DTACK will be asserted only by an CMFP
that has CS or IAK (and IEI) asserted.
This signal is not used with a 6800 pro-
cessor type.
CS :
Chip Select (input, active low). CS is u-
sed to select the TS68HC901 CMFP for
accesses to the internal registers. CS
and IACK must not be asserted at the
same time.
Data Stobe (input, active low).This Input
is part of the internal chip select and in-
terrupt acknowledge functions.
The CMFP must be located on the lower
portion of the 16-bit data-bus so that the
vector number passed to the processor
during an interrupt acknowledge cycle
will be located in the low byte of the data
word. As a result, DS must be connected
to the processor’s lower data strobe if
vectored interrupt are to be used. Note
that this forces all registers to be located
at odd addresses and latches data on the
rising edge for writes. This signal is used
as RD with an Intel processor type.
DS :
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®
TS68HC901
RS1-RS5: Register Address Bus (inputs). The ad-
(A1-A5) dress bus is used to address one of the
internal registers during a read or write
cycle.
D0-D7 : Data Bus (bi-directional, tri-stateable).
This bus is used to receive data from or
transmit data to the MFP’s internal regis-
ters during a processor read or write cy-
cle. During an interrupt acknowledge cy-
cle, the data bus is used to pass a vector
number to the processor. Since the MFP
is an 8-bit peripheral, the MFP could be
located on either the upper or lower por-
tion of the 16-bit data bus (even or odd
address). However, during an interrupt
acknowledge cycle, the vector number
passed to the processor must be located
in the low byte of the data word. As a re-
sult, D0-D7 of the MFP must be connec-
ted to the low eight bits of the processor
data bus, placing MFP registers at odd
addresses if vectored interrupt are to be
used.
CLK :
The clock input is a single-phase TTL
compatible signal used for internal ti-
ming . This input should not be gated off
at any time and must conform to mini-
mum and maximum pulse width times.
The clock is not necessarily the system
clock in frequency nor phase. When the
bus is multiplexed (MPX=1), an address
strobe signal is connected to this pin. In
the non multiplexed mode (MPX=0), this
input is connected to the system clock
when used with a 68000 processor type
or to V
SS
(0V
DC
) when used with a 6800
processor type.
RESET : Device reset. (input, active low). Reset
disables the USART receiver and trans-
mitter, stops all timers and forces the ti-
mer outputs low, disables all interrupt
channels and clears any pending inter-
rupts. The General Purpose Interrupt/I/O
lines will be placed in the tri-state input
mode. All internal registers (except the ti-
mer, USART data registers, and transmit
status register) will be cleared.
MPX :
This input selects the data bus mode:
MPX = 0 : non multiplexed mode
MPX = 1 : multiplexed mode. The register
select lines RS1-RS5 and the data bus
D0-D7 are multiplexed. An address
strobe must be connected to the CLK pin.
TR :
IRQ :
Interrupt Request (output, active low, o-
pen drain). This output signals the pro-
cessor that an interrupt is pending from
the CMFP. These are 16 interrupt chan-
nels that can generate an interrupt re-
quest. Clearing the interrupt pending re-
gisters (IPRA and IPRB) or clearing the
interrupt mask registers (IMRA and
IMRB) will cause IRQ to be negated. IRQ
will also be negated as the result of an in-
terrupt acknowledge cycle, unless addi-
tional i nterrupts are pending in the
CM FP. Ref er to paragraph INTER-
RUPTS for further information.
Interrupt Acknowledge (input, active
l ow ). IACK i s us ed t o s ignal t he
TS68HC901 that the CPU is acknow-
ledging an interrupt. CS and IACk must
not be asserted at the same time.
Interrupt Enable In (input, active low). IEI
is used to signal the TS68HC901 that no
higher priority device is requesting inter-
rupt service.
Interrupt Enable Out (output, active low).
IEO is used to signal lower priority peri-
pherals that neither the TS68HC901 nor
another higher priority peripheral is re-
questing interrupt service.
Ge neral Purpose Interrupt I/O lines.
These lines may be used as interrupt in-
puts and/or I/O lines. When used asinter-
rupt inputs, their active edge is program-
mable. A data direction register is used to
define which lines are to be Hi-Z inputs
and which lines are to be push-pull TTL
compatible outputs.
Serial Output. This is the output of the U-
SART transmitter.
Serial Input. This is the input to the U-
SART receiver.
Receiver Clock. This input controls the
serial bit rate of the USART receiver.
Transmitter Clock. This input controls the
serial bit rate of the USART transmitter.
Receiver Ready. (output, active low)
DMA output for receiver, which reflects
the status of Buffer Full in port number
15.
Transmitter Ready. (output, active low)
DMA output for transmitter, which re-
flects the status of Buffer Empty in port
number 16.
5/42
®
IACK :
IEI :
IEO :
I0-I7 :
SO :
SI :
RC :
TC :
RR :
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