Si52146
PCI-E
XPRESS
G
EN
1, G
EN
2, & G
EN
3 S
IX
O
UTPUT
C
LOCK
G
ENERATOR
Features
PCI-Express Gen 1, Gen 2, &
Gen 3 compliant
Low power push-pull type
differential output buffers
Integrated resistors on differential
clocks
Dedicated output enable pin for
each clock
Hardware selectable spread
control
Six PCI-Express clocks
25 MHz crystal input or clock
input
I
2
C support with readback
capabilities
Triangular spread spectrum
profile for maximum
electromagnetic interference
(EMI) reduction
Industrial temperature:
–40 to 85
o
C
3.3 V Power supply
32-pin QFN package
Ordering Information:
See page 18
Applications
Network attached storage
Multi-function printer
Pin Assignments
CKPWRGD_PDB
1
SDATA
26
XOUT
OE1
1
OE0
1
32
31
30
29
VDD
XIN
28
27
25
24 VDD
23 DIFF5
22 DIFF5
21 VDD
Description
The Si52146 is a spread-controlled PCIe clock generator that can source
six PCIe clocks simultaneously. The device has six hardware inputs for
enabling the respective outputs on the fly while powered on along with the
spread control hardware pin to enable Spread for EMI reduction.
VDD
OE2
1
SSON
2
OE3
1
OE4
1
OE5
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33
GND
SCLK
20
Wireless access point
Routers
DIFF4
19 DIFF4
18
DIFF3
NC
VDD
17 DIFF3
DIFF1
DIFF0
DIFF0
DIFF1
DIFF2
VDD
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
DIFF0
XIN/CLKIN
XOUT
DIFF1
Patents pending
PLL1
(SSC)
Divider
DIFF2
DIFF3
DIFF4
SCLK
SDATA
CKPWRGD/PDB
OE [5:0]
SSON
DIFF5
Control & Memory
Control
RAM
Preliminary Rev. 0.1 12/11
Copyright © 2011 by Silicon Laboratories
DIFF2
VDD
Functional Block Diagram
Si52146
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si52146
2
Preliminary Rev. 0.1
Si52146
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. CKPWRGD_PDB (Power down) Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. PDB (Power down) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.4. PDB Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.5. OE Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.6. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.7. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.8. SSON Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5. Pin Descriptions: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Preliminary Rev. 0.1
3
Si52146
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
3.3 V Operating Voltage
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Leakage Current
Input Low Leakage Current
3.3 V Output High Voltage
(SE)
3.3 V Output Low Voltage
(SE)
High-impedance Output
Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Power Down Current
Dynamic Supply Current
Symbol
VDD core
V
IH
V
IL
V
IHI2C
V
ILI2C
I
IH
I
IL
V
OH
V
OL
I
OZ
C
IN
C
OUT
L
IN
I
DD
_
PD
I
DD_3.3V
All outputs enabled. Differ-
ential clocks with 5” traces
and 2 pF load.
Test Condition
3.3 ±5%
Control input pins
Control input pins
SDATA, SCLK
SDATA, SCLK
Except internal pull-down
resistors, 0 < V
IN
< V
DD
Except internal pull-up
resistors, 0 < V
IN
< V
DD
I
OH
= –1 mA
I
OL
= 1 mA
Min
3.135
2.0
V
SS
– 0.3
2.2
—
—
–5
2.4
—
–10
1.5
—
—
—
—
Typ
3.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
3.465
V
DD
+ 0.3
0.8
—
1.0
5
—
—
0.4
10
5
6
7
1
60
Unit
V
V
V
V
V
A
A
V
V
A
pF
pF
nH
mA
mA
4
Preliminary Rev. 0.1
Si52146
Table 2. AC Electrical Specifications
Parameter
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
CLKIN Rise and Fall Times
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF at 0.7 V
DIFF Duty Cycle
Symbol
L
ACC
T
DC
T
R
/T
F
T
CCJ
T
LTJ
V
IH
V
IL
I
IH
I
IL
T
DC
Condition
Measured at V
DD
/2 differential
Measured at V
DD
/2
Measured between 0.2 V
DD
and
0.8 V
DD
Measured at VDD/2
Measured at VDD/2
XIN/CLKIN pin
XIN/CLKIN pin
XIN/CLKIN pin, VIN = VDD
XIN/CLKIN pin, 0 < VIN <0.8
Measured at 0 V differential
Measured at 0 V differential
Min
—
47
0.5
—
—
2
—
—
–35
45
—
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
250
53
4.0
250
350
VDD+0.3
0.8
35
—
55
50
Unit
ppm
%
V/ns
ps
ps
V
V
uA
uA
%
ps
Any DIFF Clock Skew from the T
SKEW(win
Earliest Bank to the Latest
dow)
Bank
DIFF Cycle to Cycle Jitter
Output PCIe Gen1 REFCLK
Phase Jitter
Output PCIe Gen2 REFCLK
Phase Jitter
Output PCIe Gen2 REFCLK
Phase Jitter
T
CCJ
RMS
GEN1
Measured at 0 V differential
Includes PLL BW 1.5–22 MHz,
ζ
= 0.54, Td=10 ns,
Ftrk=1.5 MHz with BER = 1E-12
Includes PLL BW 8–16 MHz, Jitter
Peaking = 3 dB,
ζ
= 0.54,
Td=12 ns), Low Band, F < 1.5 MHz
Includes PLL BW 8–16 MHz, Jitter
Peaking = 3 dB,
ζ
= 0.54,
Td=12 ns), High Band,
1.5 MHz < F < Nyquist
Includes PLL BW 2–4 MHz,
CDR = 10 MHz)
Measured at 0 V differential
Measured differentially from
±150 mV
—
0
35
40
50
108
ps
ps
RMS
GEN2
0
2
3.0
ps
RMS
GEN2
0
2
3.1
ps
Output Phase Jitter Impact—
PCIe Gen3
DIFF Long Term Accuracy
DIFF Rising/Falling Slew Rate
Voltage High
Voltage Low
Crossing Point Voltage at
0.7 V Swing
Enable/Disable and Setup
Clock Stabilization from
Power-up
Stopclock Set-up Time
RMS
GEN3
L
ACC
T
R
/T
F
V
HIGH
V
LOW
V
OX
0
—
1
—
–0.3
300
0.5
—
—
—
—
—
1.0
100
8
1.15
—
550
ps
ppm
V/ns
V
V
mV
T
STABLE
T
SS
—
10.0
—
—
1.8
—
ms
ns
Preliminary Rev. 0.1
5
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