TS80C31X2
8-bit CMOS Microcontroller 0-60 MHz
1. Description
TEMIC TS80C31X2 is high performance CMOS and
ROMless versions of the 80C51 CMOS single chip 8-
bit microcontroller.
The TS80C31X2 retains all features of the TEMIC
TSC80C31 with 128 bytes of internal RAM, a 5-source,
4 priority level interrupt system, an on-chip oscilator
and two timer/counters.
In addition, the TS80C31X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C31X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C31X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q
80C31 Compatible
•
8031 pin and instruction compatible
•
Four 8-bit I/O ports
•
Two 16-bit timer/counters
•
128 bytes scratchpad RAM
q
Interrupt Structure with
•
5 Interrupt sources,
•
4 priority level interrupt system
q
Full duplex Enhanced UART
•
Framing error detection
•
Automatic address recognition
q
High-Speed Architecture
•
40 MHz @ 5V, 30MHz @ 3V
•
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
q
Power Control modes
•
Idle mode
•
Power-down mode
•
Power-off Flag
q
q
Dual Data Pointer
Asynchronous port reset
q
q
q
Once mode (On-chip Emulation)
Power supply: 4.5-5.5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
o
C) and
Industrial (-40 to 85
o
C)
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1
(13.9 footprint)
q
Rev. A - Mar. 19, 1999
1
Preliminary
TS80C31X2
3. Block Diagram
RxD
XTAL1
XTAL2
ALE/ PROG
PSEN
CPU
EA
RD
WR
(1)
(1)
Timer 0
Timer 1
INT
Ctrl
Parallel I/O Ports & Ext. Bus
Port 0 Port 1 Port 2 Port 3
EUART
RAM
128x8
TxD
C51
CORE
(1) (1)
IB-bus
(1) (1)
RESET
T0
T1
(1) (1)
P1
P2
INT0
INT1
P0
P3
(1): Alternate function of Port 3
2
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories:
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
•
I/O port registers: P0, P1, P2, P3
•
Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
•
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
•
Power and clock control registers: PCON
•
Interrupt system registers: IE, IP, IPH
•
Others: CKCON
Table 1. All SFRs with their address and their reset value
Bit
address-
able
0/8
1/9
2/A
3/B
Non Bit addressable
4/C
5/D
6/E
7/F
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
IP
XXX0 0000
P3
1111 1111
IE
0XX0 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
0/8
TMOD
0000 0000
SP
0000 0111
1/9
TL0
0000 0000
DPL
0000 0000
2/A
TL1
0000 0000
DPH
0000 0000
3/B
4/C
5/D
6/E
TH0
0000 0000
TH1
0000 0000
CKCON
XXXX XXX0
PCON
00X1 0000
7/F
SBUF
XXXX XXXX
SADDR
0000 0000
AUXR1
XXXX 0XX0
SADEN
0000 0000
IPH
XXX0 0000
PSW
0000 0000
ACC
0000 0000
B
0000 0000
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
reserved
Rev. A - Mar. 19, 1999
3
Preliminary
TS80C31X2
5. Pin Configuration
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0
VSS1/NIC*
P0.2/AD2
P0.3/AD3
39
38
37
36
35
34
33
32
31
30
29
P0.0/AD0
P0.1/AD1
P0.1
P0.2
P1.4
P1.3
P1.2
P1.1
P1.0
2
P0.3
P0.4
P0.5
P0.6
P0.7
EA
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
1
44 43 42 41 40
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
PDIL40
PLCC44
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR
NIC*
P2.0/A8
XTAL2
XTAL1
P2.2/A10
P2.3/A11
P2.4/A12
P3.7/RD
P2.1/A9
VSS
VSS1/NIC*
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 43
42 41 40
39
38 37 36 35 34
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
PQFP44
VQFP44
12 13 14 15 16 17 18 19 20 21 22
XTAL1
NIC*
P2.0/A8
XTAL2
P2.3/A11
P2.4/A12
P2.1/A9
VSS
P2.2/A10
P3.6/WR
P3.7/RD
*NIC: No Internal Connection
4
P0.3/AD3
VCC
P1.4
P1.3
P1.2
P1.1
P1.0
VCC
Rev. A - Mar. 19, 1999
Preliminary
TS80C31X2
Table 2. Pin Description for 40/44 pin packages
MNEMONIC
V
SS
Vss1
V
CC
P0.0-P0.7
PIN NUMBER
DIL
20
LCC
22
1
44
43-36
VQFP 1.4
16
39
38
37-30
TYPE
I
I
I
I/O
NAME AND FUNCTION
Ground:
0V reference
Optional Ground:
Contact the Sales Office for ground connection.
Power Supply:
This is the power supply voltage for normal, idle and power-
down operation
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during access to external program
and data memory. In this application, it uses strong internal pull-up when emitting
1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups.
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Port 3 also serves the special
features of the 80C51 family, as listed below.
RXD (P3.0):
Serial input port
TXD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt 0
INT1 (P3.3):
External interrupt 1
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V
SS
permits a power-on reset
using only an external capacitor to V
CC.
Address Latch Enable:
Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped during each
access to external data memory.
Program Store ENable:
The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
External Access Enable:
EA must be externally held low to enable the device
to fetch code from external program memory locations.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier
40
39-32
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
P2.0-P2.7
21-28
24-31
18-25
I/O
P3.0-P3.7
10-17
11,
13-19
5,
7-13
I/O
10
11
12
13
14
15
16
17
9
11
13
14
15
16
17
18
19
10
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I
Reset
ALE
30
33
27
O (I)
PSEN
29
32
26
O
EA
XTAL1
XTAL2
31
19
18
35
21
20
29
15
14
I
I
O
Rev. A - Mar. 19, 1999
5
Preliminary
FPGA/CPLD
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