3226 is a 2-cell series supercapacitor charger with
a backup PowerPath controller. It includes a charge pump
supercapacitor charger with programmable output voltage,
a low dropout regulator, and a power-fail comparator for
switching between normal and backup modes.
The constant input current supercapacitor charger is
designed to charge two supercapacitors in series to a
resistor-programmable output voltage from a 2.5V to 5.3V
input supply. The charger input current limit is program-
mable by an external resistor at up to 315mA.
The internal backup LDO is powered from the superca-
pacitors and provides up to 2A peak output current with
an adjustable output voltage. When the input supply falls
below the power-fail threshold, the LTC3226 automatically
enters a backup state in which the supercapacitors power
the output through the LDO. The input supply power-fail
voltage level is programmed by an external resistor divider.
Low input noise, low quiescent current and a compact
footprint make the LTC3226 ideally suited for small, battery-
powered applications. Internal current limit and thermal
shutdown circuitry allow the device to survive a continu-
ous short-circuit from the PROG or CPO pins to ground.
n
n
n
n
n
n
n
1x/2x Multimode Charge Pump Supercapacitor
Charger
Automatic Cell Balancing
Ideal Diode Main PowerPath™ Controller
(V
IN
to V
OUT
)
Internal 2A LDO Backup Supply (CPO to V
OUT
)
Automatic Main/Backup Switchover
Input Voltage Range: 2.5V to 5.5V
Programmable SCAP Charge Voltage
Programmable Input Current Limit (315mA Max)
No Load I
VIN
= 55μA (Typical)
Low Profile, 16-Lead 3mm
×
3mm QFN Package
APPLICATIONS
n
n
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n
n
n
Smart Power Meters
Battery-Powered Industrial/Medical Equipment
3.3V Solid-State Drives
Industrial Alarms
Data Backup Supplies
Battery Hold-Up Supplies
L,
LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
3.3V Backup Supply
MPEXT
TO LOAD
(2A)
LTC3226
LDO
V
IN
3.3V
2.2µF
1.96M
1.2V
PFI
1.21M
2.2µF
C
+
C
–
PROG
33.2k
EN_CHG
PFO
RST
CAPGOOD
Automatic Normal-to-Backup
Mode Switchover
6
C
OUT
47µF
VOLTAGE (V)
5
4
3
2
1
CPO
C
SC
= 1.2F
C
OUT
= 47µF
I
LOAD
= 2A
V
OUT
V
IN
BACKUP
BACKUP MODE
MODE
(LDO IN
(LDO IN
REGULATION) DROPOUT)
PFO
(2V/DIV)
0
0.4
0.8
1.2
TIME (SECONDS)
1.6
2.0
3226 TA01b
V
IN
GATE
V
OUT
LDO_FB
255k
80.6k
5V
C
SC
1.2F
3.83M
1.21M
+
–
RST_FB
CPO
VMID
CHARGE
PUMP
CPO_FB
V
IN
0
–1
GND
3226 TA01a
3226f
1
LTC3226
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
TOP VIEW
VMID
CPO
V
IN
12 C
–
17
GND
11 CAPGOOD
10 CPO_FB
9
5
GATE
6
RST_FB
7
RST
8
EN_CHG
PROG
C
+
16 15 14 13
V
OUT
1
PFO
2
PFI 3
LDO_FB 4
V
IN
, V
OUT
, VMID, CPO,
RST, PFO,
CAPGOOD, LDO_FB ..................................... –0.3V to 6V
EN_CHG, PFI, RST_FB,
CPO_FB Voltage ............–0.3V to Max (V
IN
, CPO) + 0.3V
Operating Junction Temperature ................ –40 to 125°C
Storage Temperature Range ......................–65 to 150°C
UD PACKAGE
16-LEAD (3mm
×
3mm) PLASTIC QFN
T
JMAX
= 125°C,
θ
JA
= 58.7°C/W (NOTE 2)
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3226EUD#PBF
LTC3226IUD#PBF
TAPE AND REEL
LTC3226EUD#TRPBF
LTC3226IUD#TRPBF
PART MARKING*
LFZV
LFZV
PACKAGE DESCRIPTION
16-Lead (3mm
×
3mm) Plastic QFN
16-Lead (3mm
×
3mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
3226f
2
LTC3226
ELECTRICAL CHARACTERISTICS
SYMBOL
V
IN
I
VIN(ST)
I
CPO(ST)
I
VOUT(ST)
I
CPO(BU)
I
VOUT(BU)
PARAMETER
Input Supply Range
V
IN
Quiescent Current in Normal Mode
CPO Quiescent Current in Normal Mode
V
OUT
Quiescent Current in Normal Mode
CPO Quiescent Current in Backup Mode
V
OUT
Quiescent Current in Backup Mode
V
PFI
> 1.2V, V
CPO_FB
> 1.2V, V
IN
< V
CPO
V
PFI
> 1.2V, V
CPO_FB
> 1.2V, V
IN
< V
CPO
V
OUT
= V
IN
, V
PFI
> 1.2V, V
CPO_FB
> 1.2V,
V
IN
< V
CPO
V
PFI
< 1.2V, V
LDO_FB
> 0.8V, V
CPO
> V
OUT
V
IN
= 0V, V
PFI
< 1.2V, V
LDO_FB
> 0.8V,
V
CPO
> V
OUT
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C (Note 3). V
IN
= 3.3V, V
CPO
= 5V, V
OUT
= 3.3V, VMID = 1/2 V
CPO
unless
otherwise noted.
CONDITIONS
l
MIN
2.5
TYP
10
20
5
24
3
MAX
5.5
UNITS
V
µA
µA
µA
µA
µA
Ideal Diode Controller
V
FWD(EDA)
V
RTO
External Ideal Diode Forward Voltage (V
IN
-V
OUT
) I
VOUT
= 2mA
Fast Turn-Off Voltage (V
IN
-V
OUT
)
Fast Turn-On Voltage (V
IN
-V
OUT
)
Charge Pump Supercapacitor Charger
V
CPO_FB
I
CPO_FB
f
OSC
R
OL
V
PROG
I
VIN(ILIM)
h
PROG
I
CHRG(1x)
I
CHRG(2x)
I
SC
V
MODE
CPO_FB Pin Threshold for Entering Sleep Mode
CPO_FB Pin Hysteresis for Exiting Sleep Mode
Charge Pump FB Pin Input Leakage
CLK Frequency
Effective Open-Loop Output Impedance (Note 4) V
CPO
= 4.5V, C
FLY
= 1µF
PROG Pin Servo Voltage
Input Current Limit
Ratio of V
IN
Input Current Limit to PROG Pin
Current
CPO Pin Charging Current (1x Mode)
CPO Pin Charging Current (2x Mode)
Short-Circuit Charge Current
V
IN
to CPO Voltage Differential for Switching
Mode from 1x to 2x
1x/2x Mode Comparator Hysteresis
V
CLAMP
V
STACK
VMID
Maximum Voltage Across Either Supercapacitor
After Charging
Maximum Supercapacitor Stack Voltage
VMID Output Voltage
VMID Current Sourcing Capability
VMID Current Sinking Capability
CPO_FB Pin Threshold Voltage (Rising) for
CAPGOOD
CPO_FB Pin Hysteresis for CAPGOOD
CAPGOOD Output Low Voltage
CAPGOOD High Impedance Leakage Current
I
SINK
= 5mA
V
CAPGOOD
= 5V
l
l
l
l
15
–45
45
1.18
–50
0.75
0.9
6
l
mV
mV
mV
1.24
50
1.05
1.02
V
mV
nA
MHz
Ω
V
mA
A/A
mA
mA
mA
mV
mV
2.75
5.5
V
V
V
mA
mA
1.13
V
mV
mV
1
µA
V
IN
Falling
V
OUT
Falling
1.21
20
V
CPO_FB
= 1.3V
l
V
CPO_FB
< 1.2V
R
PROG
= 33.3k, V
CPO
= 0V
R
PROG
= 33.3k, V
CPO
= 0V
V
IN
= 3.8V, R
PROG
= 33.3k, V
CPO
= 3V
R
PROG
= 33.3k
PROG Pin Grounded, V
CPO
= 0V
0.98
1.0
360
10,500
315
157.5
600
200
120
2.65
5.3
2.5
4.5
5.5
VMID < V
CPO
/2, V
CPO_FB
> 1.24V
VMID > V
CPO
/2, V
CPO_FB
> 1.24V
l
1.09
1.11
20
65
3226f
3
LTC3226
ELECTRICAL CHARACTERISTICS
SYMBOL
LDO
Minimum CPO Voltage for LDO Operation
V
LDO_FB
LDO FB Servo Voltage
Load Regulation ΔV
LDO_FB
/ΔI
OUT
LDO FET R
DS(ON)
I
LDO_FB(LEAK)
LDO_FB Input Leakage Current
I
LIM
RST_FB,
RST
V
RST_FB(TH)
V
RST_FB(HYS)
I
RST_FB(LEAK)
RST_FB Threshold (Falling Edge)
RST_FB Hysteresis
RST_FB Input Leakage Current
RST
Output Low Voltage
RST
High Impedance Leakage Current
RST
Delay (RST_FB Rising)
Power-Fail Comparator
V
PFI(TH)
V
PFI(HYS)
I
PFI(LEAK)
I
PFO(LEAK
)
EN_CHG
V
IH
V
IL
I
IH
I
IL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
l
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C (Note 3). V
IN
= 3.3V, V
CPO
= 5V, V
OUT
= 3.3V, VMID = 1/2 V
CPO
unless
otherwise noted.
PARAMETER
CONDITIONS
MIN
2.4
I
VOUT
= 1mA
1mA < I
VOUT
< 2A
V
CPO
= 3.6V
V
LDO_FB
= 0.9V
l
l
TYP
MAX
UNITS
V
0.76
0.8
2.7
200
0.82
V
mV/A
mΩ
–60
2
0.72
–50
65
4
0.74
20
60
nA
A
LDO Current Limit
0.76
50
1
V
mV
nA
mV
µA
ms
V
RST_FB
= 0.9V
I
SINK
= 5mA
V
RST
= 5V
l
l
290
l
PFI Input Threshold (Falling Edge)
PFI input Hysteresis
PFI Input Leakage Current
PFO
Output Low Voltage
PFO
High Impedance Leakage Current
PFI Delay to
PFO
(PFI Falling)
V
PFI
= 0.5V
I
SINK
= 5mA
V
PFO
= 5V
1.175
–50
1.2
20
1.225
50
V
mV
nA
mV
µA
µs
V
l
65
l
1
0.5
1.3
0.4
–1
–1
1
1
V
µA
µA
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Failure to solder the exposed backside of the package to the PC
board ground plane will result in a thermal resistance much greater than
58.7°C/W.
Note 3:
The LTC3226E is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3226I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The junction temperature, T
J
, is calculated from the
ambient temperature, T
A
, and power dissipation, P
D
, according to the
formula:
T
J
= T
A
+ (P
D
• 58.7°C/W)
Note that the maximum ambient temperature, consistent with these
specifications, is determined by specific operating conditions in
conjunction with board layout, the rated thermal package thermal
FPGA/CPLD
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