INTEGRATED CIRCUITS
74F269
8-bit bidirectional binary counter
Product specification
IC15 Data Handbook
1996 Jan 05
Philips
Semiconductors
Philips Semiconductors
Product specification
8–bit bidirectional binary counter
74F269
FEATURES
•
Synchronous counting and loading
•
Built-in look-ahead carry capability
•
Count frequency 115MHz typ
•
Supply current 95mA typ
DESCRIPTION
The 74F269 is a fully synchronous 8-stage Up/Down Counter
featuring a preset capability for programmable operation, carry
look-ahead for easy cascading and a U/D input to control the
direction of counting. All state changes, whether in counting or
parallel loading, are initiated by the rising edge of the clock.
TYPICAL
SUPPLY CURRENT
(TOTAL)
95mA
PIN CONFIGURATION
U/D 1
Q0
Q1
Q2
Q3
Q4
GND
Q5
Q6
2
3
4
5
6
7
8
9
24 PE
23 P0
22 P1
21 P2
20 P3
19 V
CC
18 P4
17 P5
16 P6
15 P7
14 TC
13 CET
Q7 10
CP 11
CEP 12
TYPE
74F269
TYPICAL f
MAX
115MHz
SF00834
ORDERING INFORMATION
DESCRIPTION
24-Pin Plastic Slim DIP (300mil)
24-Pin Plastic SOL
24-Pin Plastic SSOP type II
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F269N
N74F269D
N74F269DB
PKG DWG #
SOT222-1
SOT137-1
SOT340-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
P0 - P7
PE
U/D
CEP
CET
CP
TC
Q0 - Q7
Parallel Data inputs
Parallel Enable input (active Low)
Up/Down count control input
Count Enable Parallel input (active Low)
Count Enable Trickle input (active Low)
Clock input
Terminal Count output (active Low)
Flip-flop outputs
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1.0mA/20mA
NOTE:
One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
1996 Jan 05
2
853–0056 16186
Philips Semiconductors
Product specification
8–bit bidirectional binary counter
74F269
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
CTR DIV 256
24
1
12
13
&
EN6
2, 3, 5, 6 +/C7
2, 4, 5, 6–
2
3
4
5
6
8
9
10
14
G5
M1[LOAD]
M2[COUNT]
M3[UP]
M4[DOWN]
23
22
21
20
18
17
16
15
P0
24
1
12
13
11
PE
U/D
CEP
CET
CP
Q0
P1
P2
P3
P4
P5
P6
P7
11
23
TC
14
22
21
20
Q1
Q2
Q3
Q4
Q5
Q6
Q7
18
17
2
3
4
5
6
8
9
10
16
15
1, 7D [1]
[2]
[4]
[8]
[16]
[32]
[64]
[128]
3, 5, 6 CT=256
4, 5, 8 CT=0
V
CC
=Pin 19
GND=Pin 7
SF00835
SF00836
APPLICATION
CP
U/D
PE
P0 P1 P2 P3 P4 P5 P6 P7
PE
U/D
CP
CEP
TC
P0 P1 P2 P3 P4 P5 P6 P7
PE
U/D
CP
TC
CEP
CET
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
P0 P1 P2 P3 P4 P5 P6 P7
PE
U/D
CP
TC
CEP
CET
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
P0 P1 P2 P3 P4 P5 P6 P7
PE
U/D
CP
TC
CEP
CET
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CET
Q
0
Q1 Q2 Q3 Q4 Q5 Q6 Q7
Least significant 8-bit counter
Most significant 8-bit counter
SF00851
Figure 1. Synchronous Multistage Counting Scheme
MODE SELECT FUNCTION TABLE
INPUTS
CP
↑
↑
↑
↑
↑
↑
H =
h =
L =
l =
q =
X =
↑
=
(a) =
U/D
X
X
h
l
X
X
CEP
X
X
l
l
h
X
CET
X
X
l
l
l
h
PE
l
l
h
h
h
h
P
n
l
h
X
X
X
X
OUTPUTS
Q
n
L
H
Count Up
Count Down
q
n
q
n
TC
(a)
(a)
(a)
(a)
(a)
H
OPERATING MODE
Parallel load
Count Up
Count Down
Hold (do nothing)
High voltage level
High voltage level one setup prior to the Low-to-High clock transition
Low voltage level
Low voltage level one setup time prior to the Low-to-High clock transition
Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition
Don’t care
Low-to-High clock transition
TC is Low when CET is Low and the counter is at Terminal Count. Terminal Count Up is with all Q
n
outputs High and Terminal Count
Down is with all Qn outputs Low.
1996 Jan 05
3
Philips Semiconductors
Product specification
8–bit bidirectional binary counter
74F269
LOGIC DIAGRAM
2
P0 23
DETAIL A
Q0
P1
22
3
DETAIL A
Q1
P2
21
DETAIL A
4 Q2
P3
20
5
DETAIL A
Q3
6
P4 18
DETAIL A
Q4
P5
17
8
DETAIL A
Q5
9
P6 16
DETAIL A
Q6
10
P7 15
DETAIL A
Q7
PE 24
CP 11
1
U/D
CEP 12
CET
13
14
TOGGLE
DETAIL A
Pn
TC
D
CP
Q
Q
PE
V
CC
=Pin 19
GND=Pin 7
CP
SF00837
1996 Jan 05
4
Philips Semiconductors
Product specification
8–bit bidirectional binary counter
74F269
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–1
20
70
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
°C
UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
SYMBOL
PARAMETER
TEST
CONDITIONS
NO TAG
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
MIN
2.5
V
2.7
3.4
0.30
0.30
–0.73
0.50
V
0.50
–1.2
100
20
–0.6
–60
PE=CET=CEP=U/D=GND,
Pn=4.5V, CP=↑
PE=CET=CEP=U/D=GND,
Pn=GND, CP=↑
93
98
–150
120
125
V
µA
µA
mA
mA
mA
mA
TYP
NO TAG
MAX
UNIT
V
O
OH
High-level
High level output voltage
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OH
= MAX
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OS
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level input current
Short-circuit output current
NO TAG
I
CCH
V
CC
= MIN, V
IL
= MAX
V
IH
= MIN, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
=
MAX
I
CC
Supply current (total)
I
CCL
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
1996 Jan 05
5
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