The MICRF505 is a true single-chip, frequency shift
keying (FSK) transceiver intended for use in half-
duplex, bidirectional RF links. The multi-channeled
FSK transceiver is intended for UHF radio
equipment in compliance with the North American
Federal Communications Commission (FCC) part
15.247 and the European Telecommunication
Standard Institute (ETSI) specification, EN300 220.
The transmitter consists of a PLL frequency
synthesizer and power amplifier. The frequency
synthesizer consists of a voltage-controlled oscillator
(VCO), a crystal oscillator, dual modulus prescaler,
programmable frequency dividers, and a phase-
detector. The loop-filter is external for flexibility and
can be a simple passive circuit. The output power of
the power amplifier can be programmed to seven
levels. A lock-detect circuit detects when the PLL is
in lock. In receive mode, the PLL synthesizer
generates the local oscillator (LO) signal. The N, M,
and A values that give the LO frequency are stored
in the N0, M0, and A0 registers.
The receiver is a zero intermediate frequency (IF)
type which makes channel filtering possible with low-
power, integrated low-pass filters. The receiver
consists of a low noise amplifier (LNA) that drives a
quadrature mix pair. The mixer outputs feed two
identical signal channels in phase quadrature. Each
channel includes a pre-amplifier, a third order
Sallen-Key RC low-pass filter that protects the
following switched-capacitor filter from strong
adjacent channel signals, and a limiter. The main
channel filter is a switched-capacitor implementation
of a six-pole elliptic low pass filter. The cut-off
frequency of the Sallen-Key RC filter can be
programmed to four different frequencies: 100kHz,
150kHz, 230kHz, and 340kHz. The I and Q channel
outputs are demodulated and produce a digital data
output. The demodulator detects the relative phase
of the I and the Q channel signal. If the I channel
signal lags behind the Q channel, the FSK tone
frequency is above the LO frequency (data '1'). If the
I channel leads the Q channel, the FSK tone is
below the LO frequency (data '0'). The output of the
receiver is available on the DataIXO pin. A receive
signal strength indicator (RSSI) circuit indicates the
received signal level. All support documentation can
be found on Micrel’s web site at www.micrel.com.
October 2006
1
RadioWire®
Features
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True single chip transceiver
Digital bit synchronizer
Received signal strength indicator (RSSI)
RX and TX power management
Power down function
Reference crystal tuning capabilities
Frequency error estimator
Baseband shaping
Three-wire programmable serial interface
Register read back function
Applications
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Telemetry
Remote metering
Wireless controller
Remote data repeater
Remote control systems
Wireless modem
Wireless security system
M9999-103106
+1 408-944-0800
Micrel
MICRF505BML/YML
General Description ................................................................................................................................................... 1
Features ..................................................................................................................................................................... 1
Ordering Information .................................................................................................................................................. 4
Writing to the control registers in MICRF505 ........................................................................................................... 10
Writing to a Single Register ..................................................................................................................................... 10
Writing to All Registers............................................................................................................................................. 11
Writing to n Registers having Incremental Addresses ............................................................................................. 11
Writing to n Registers having Non-Incremental Addresses ..................................................................................... 12
Reading from the control registers in MICRF505 .................................................................................................... 12
Power on Reset........................................................................................................................................................ 13
Frequency Synthesizer ............................................................................................................................................ 15
Modes of Operation .............................................................................................................................................. 18
Data Interface........................................................................................................................................................... 19
Front End.............................................................................................................................................................. 20
Bit Synchronizer ................................................................................................................................................... 23
Power Amplifier .................................................................................................................................................... 24
Using the XCO-tune Bits .......................................................................................................................................... 28
MICRF505BML/YML Land pattern........................................................................................................................... 31
Package Information MICRF505BML ...................................................................................................................... 33
Package Information MICRF505YML ...................................................................................................................... 34
Overview of programming bit ................................................................................................................................... 35
Table 1: Detailed description of programming bit .................................................................................................... 35
Table 2: Main Mode bit............................................................................................................................................. 40
Table 3: Synchronizer mode bit ............................................................................................................................... 40
Table 5: Prefilter bit .................................................................................................................................................. 40
Table 6: Power amplifier bit ..................................................................................................................................... 41
Table 8: Test signals ................................................................................................................................................ 41
Table 10: Frequency Error Estimation control bit .................................................................................................... 42
Table 11: Frequency Error Estimation control bit, cont............................................................................................ 42
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