MIC2592B
Dual-Slot PCI Express Hot-Plug Controller
General Description
The MIC2592B is a dual-slot power controller supporting the
power distribution requirements for Peripheral Component
Interconnect Express (PCI Express) Hot-Plug compliant
systems. The MIC2592B provides complete power control
support for two PCI Express slots, including the 3.3VAUX
defined by the PCI Express standards. Support for 12V, 3.3V,
and 3.3VAUX supplies is provided including programmable
constant-current inrush limiting, voltage supervision, pro-
grammable current limit, and circuit breaker functions. These
features provide comprehensive system protection and fault
isolation. The MIC2592B also incorporates an SMBus interface
via which complete status of each slot is provided.
All support documentation can be found on Micrel’s web site
at www.micrel.com.
Features
• Supports two independent PCI Express slots
• SMBus interface for slot power control and status
• Voltage-tolerant I/O for compatibility with SMBus 2.0
systems
• 12V, 3.3V, and 3.3VAUX supplies supported per PCI
Express Specification v1.0a
- Intergrated power MOSFETs for 3.3VAUX rails
3.3V
- Standby operation for Wake-on-LAN applications with
low backfeed on Main +12V and +3.3V rails.
• Programmable inrush current limiting
• Active current regulation controls inrush current
• Electronic circuit breaker for each supply to each slot
• High accuracies for both circuit breaker trip points and
nuisance trip prevention timers
• Dual level fault detection for quick fault response without
nuisance tripping
• Thermal isolation between circuitry for Slot A and Slot B
• Two General Purpose Input pins suitable for interface to
logic and switches.
Ordering Information
MIC2592B – 2BTQ
Part Number
Standard
Pb-Free
MIC2592B – 2YTQ
12V and 3V
Fast-Trip Thresholds
100mV
150mV
Disabled
3.3VAUX
Current Limit
0.375A
0.375A
0.375A
Package
48 Pin TQFP
48 Pin TQFP
48 Pin TQFP
MIC2592B – 3BTQ* MIC2592B – 3YTQ*
MIC2592B – 5BTQ* MIC2592B – 5YTQ*
* Contact factory for availability
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2005
1
M9999-033105
MIC2592B
Micrel
Typical Application
+12V
System
Power +3.3V
Supply
VSTBY
0.1µF
0.1µF
11
26
PCI Express Connector
PCI
Express
Bus
VSTBYA VSTBYB
20
VAUXA
12VINA
15
0.1F
110k
1%
2
RFILTER[A&B]
5
12VSENSEA
CFILTERA
CFILTERB
12VGATEA
12VOUTA
8
V
STBY
C1
C2
100k
35
3
#
C
GS
22nF
#
*R
12VGATEA
15
R
SENSE
0.020
3.3AUX
375mA
100k
/FORCE_ONA
/FORCE_ONB
GPI_A0
GPI_B0
100k
100k
10
12
C
MILLER
6800pF
Si4435DY
12V
2.1A (x4/x8)
R
SENSE
0.013
9
28
4
38
/FORCE_ONA
/FORCE_ONB
GPI_A0
GPI_B0
3VINA
0.1F
13
3VSENSEA
3VGATEA
3VOUTA
MIC2592B
V
STBY
14
16
#
*R
3VGATEA
15
C
GATE
22nF
0.1F
Si4420DY
3.3V
3.0A
10k x 4
AUXENA
AUXENB
ONA
ONB
V
STBY
Hot-Plug
Controller
10k x 4
/PWRGDA
/PWRGDB
/FAULTA
/FAULTB
6
31
1
36
45
42
44
43
12VINB
AUXENA
AUXENB
ONA
ONB
12VSENSEB
32
29
C
GS
22nF
12VGATEB
12VOUTB
34
#
R
SENSE
0.020
*R
12VGATEB
15
#
27
C
MILLER
6800pF
0.1F
Si4435DY
12V
2.1A (x4/x8)
R
SENSE
0.013
/PWRGDA
/PWRGDB
/FAULTA
/FAULTB
3VINB
3VSENSEB
3VGATEB
25
24
23
21
22
17
33
46
#
*R
3VGATEB
15
Si4420DY
3.3V
3.0A
41
SMBus
Base
Address
V
STBY
A0
A1
A2
/INT
SCL
SDA
40
39
37
47
48
3VOUTB
VAUXB
GND
GND
GND
C
GATE
22nF
3.3AUX
375mA
PCI
Express
Bus
PCI Express Connector
10k x 3
SDA
SMBus I/O
SCL
/INT
SDA
SCL
/INT
Management
Controller
* Values for R
12VGATE[A/B]
and R
3VGATE[A/B]
may vary
#
depending upon the CGS of the external MOSFETs.
These components are not required for MIC2592B
operation but can be implemented for GATE output
slew rate control (application specific)
¥ Bold lines indicate high current paths
March 2005
2
M9999-033105
MIC2592B
Micrel
Pin Configuration
Hot-Plug
Control
Interface
SDA
SCL
GND
AUXENA
ONA
ONB
AUXENB
A0
A1
A2
GPI_B0
/INT
48 47 46 45 44 43 42 41 40 39 38 37
/FAULTA
CFILTERA
12VGATEA
GPI_A0
12VINA
/PWRGDA
NC
12VSENSEA
/FORCE_ONA
12VOUTA
VSTBYA
3VINA
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
3VSENSEA
3VGATEA
VAUXA
3VOUTA
GND
NC
NC
RFILTER[A&B]
3VOUTB
VAUXB
3VGATEB
3VSENSEB
36
35
34
33
32
31
30
29
28
27
26
25
/FAULTB
CFILTERB
12VGATEB
GND
12VINB
/PWRGDB
NC
12VSENSEB
/FORCE_ONB
12VOUTB
VSTBYB
3VINB
Slot A
Interface
Slot B
Interface
48-Pin TQFP
March 2005
3
M9999-033105
MIC2592B
Micrel
Pin Description
Pin Number
5
32
Pin Name
12VINA
12VINB
Pin Function
12V Supply Power and Sense Inputs [A/B]: Two pins are provided for Kelvin.
connection (one for each slot). Pin 5 is the (+) Kelvin-sense connection to
the supply side of the sense resistor for 12V Slot A. Pin 32 is the (+) Kelvin
sense connection to the supply side of the sense resistor for 12V Slot B.
These two pins must ultimately connect to each other as close as possible at
the MIC2592B controller in order to eliminate any IR drop between these
pins. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
3.3V Supply Power and Sense Inputs [A/B]: Two pins are provided for
connection (one for each slot). Pin 12 is the (+) Kelvin-sense connection to
the supply side of the sense resistor for 3V Slot A. Pin 25 is the (+) Kelvin
sense connection to the supply side of the sense resistor for 3V Slot B.
These two pins must ultimately connect to each other as close as possible at
the MIC2592B controller in order to eliminate any IR drop between these
pins. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to
monitor the 3.3V output voltages for Power-is-Good status.
12V Power-Good Sense Inputs: Connect to 12V[A/B] outputs. Used to
monitor the 12V output voltages for Power-is-Good status.
12V Circuit Breaker Sense Inputs: The current limit thresholds are set
by connecting sense resistors between these pins and 12VIN[A/B]. When
the current limit threshold of IR = 50mV is reached, the 12VGATE[A/B] pin
is modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded
for t
FLT
, the circuit breaker is tripped and the GATE pin for the affected 12V
supply’s external MOSFET is immediately pulled high.
3V Circuit Breaker Sense Inputs: The current limit thresholds are set by
connecting sense resistors between these pins and 3VIN[A/B]. When the
current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is
modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded
for t
FLT
, the circuit breaker is tripped and the GATE pin for the affected 3V
supply’s external MOSFET is immediately pulled low.
12V Gate Drive Outputs: Each pin connects to the gate of an external
P-Channel MOSFET. During power-up, the C
GATE
and the C
GS
of the
MOSFETs are connected to a 25µA current sink. This controls the value of
dv/dt seen at the source of the MOSFETs.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
FLT
. Whenever an
overcurrent, thermal shutdown, or input undervoltage fault condition occurs,
the GATE pin for the affected slot is immediately brought high. These pins
are charged by an internal current source during power-down. Also, the 3V
supply for the affected slot is shut-down.
3V Gate Drive Outputs: Each pin connects to the gate of an external
N-Channel MOSFET. During power-up, the C
GATE
and the C
GS
of the
MOSFETs are connected to a 25µA current source. This controls the value
of dv/dt seen at the source of the MOSFETs, and hence the current flowing
into the load capacitance.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
FLT
. Whenever an
overcurrent, thermal shutdown, or input undervoltage fault condition occurs,
the GATE pin for the affected slot is immediately brought low. During power-
down, these pins are discharged by an internal current source. Also, the 12V
supply for the affected slot is shut down.
12
25
3VINA
3VINB
16
21
10
27
8
29
3VOUTA
3VOUTB
12VOUTA
12VOUTB
12VSENSEA
12VSENSEB
13
24
3VSENSEA
3VSENSEB
3
34
12VGATEA
12VGATEB
14
23
3VGATEA
3VGATEB
March 2005
4
M9999-033105
MIC2592B
Micrel
Pin Name
VSTBYA
VSTBYB
Pin Function
3.3V Standby Input Voltage: Required to support PCI Express VAUX output.
Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
to ensure that the chip is accessible during standby modes. A UVLO circuit
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
threshold. Both pins must be externally connected together at the MIC2592B
controller.
3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect
the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
400mΩ MOSFETs. These outputs are current limited and protected against
short-circuit faults.
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
these controls only after the V
STBY
input supply is valid and stabe (i.e., t
POR
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
these pins to GND if using SMI power control. Also, see pin description for
/FAULTA and /FAULTB.
Enable Inputs: Rising-edge triggered. Used to enable or disable the
VAUX[A/B] outputs. The outputs can be switched on by these controls only
after the V
STBY
input supply is valid and stabe (i.e., t
POR
elapses - See the
Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
SMI power control. Also, see pin description for /FAULTA and /FAULTB.
Overcurrent Timers: Capacitors connected between these
pins and GND set the duration of t
FLT
for each slot. The overcurrent filter
delay (t
FLT
) is the amount of time for which a slot remains in current limit
before its circuit breaker is tripped.
/PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has
been commanded to turn on and has successfully begun delivering power to
its respective +12V, +3.3V, and VAUX outputs. Each pin requires an external
extern
pull-up resistor to V
STBY
.
/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the
circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to V
STBY
.
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
was asserted in response to a fault condition on one of the slot’s MAIN out-
puts (+12V or +3.3V).
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] was asserted in response to a fault condition on the slot’s
VAUX output. If a fault condition occurred on both the MAIN and VAUX
outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be
brought low to deassert the /FAULT[A/B] output.
Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
VAUX), while specifically defeating all protections on those supplies. This
explcitly includes all overcurrent and short circuit protections, and on-chip
thermal protection for the VAUX[A/B] supplies. Additionally included are the
UVLO protections for the +3.3V and +12V main supplies. The
/FORCE_ON[A/B] pins do not disable UVLO protection for the VAUX[A/B]
supplies. These input pins are intended for diagnostic purposes only.
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
register set will continue to reflect the actual state of each slot’s supplies.
There is a pair of register bits, accessible via the SMBus, which can be set
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
pins -- See CNTRL[A/B] Register Bit D[2].
General Purpose Inputs: The states of these two inputs are available by
reading the Common Status Register, Bits [4:5]. If not used, connect each
pin to GND.
Pin Description (continued)
Pin Number
11
26
15
22
VAUXA
VAUXB
44
43
ONA
ONB
45
42
AUXENA
AUXENB
2
35
CFILTERA
CFILTERB
6
31
/PWRGDA
/PWRGDB
1
36
/FAULTA
/FAULTB
9
28
/FORCE_ONA
/FORCE_ONB
4
38
GPI_A0
GPI_B0
March 2005
5
M9999-033105
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
