TS823/824/825
Microprocessor Supervisory Circuit with
Watchdog Timer & Manual Reset
7 Voltage Threshold Voltage Option
From 2.19V ~ 4.63V
General Description
The TS823/824/825 family allows the user to customize the CPU monitoring function without any external components.
The user has a large choice of reset voltage thresholds and output driver configurations, all of which are present ant
the factory. Each wafer is trimmed to the customer’s specifications.
These circuits will ignore fast negative going transients on Vdd. The state of the reset output is guaranteed to be
correct down to 1V. After Vdd crosses above a factory present threshold, the TS823/824/825 assert a reset signal.
After a predetermined time (the “reset” interval) the reset is deasserted. If Vdd ever drops below the threshold voltage
a reset is asserted immediately. In addition to a supply monitoring function the TS823/824/825 also monitor transitions
at the watchdog (WDI) input. If a logic transition does not occur at the WDI pin within a certain time interval (the
“watchdog” interval) then a reset is asserted. The reset deasserts after the reset interval, as explained earlier.
The TS823/824/825 can both assert a reset manually by pulling the MR input to ground, and the micro-power
quiescent current make this family a natural for portable battery powered equipment.
The TS823/824/825 is available in a 5-pin SOT-25 package.
Features
Precision monitoring of +3V, +3.3V and +5V
power supply voltage
Tight voltage threshold tolerance +/-1.5%
Fully specified over temperature
210mS min. power-on reset pulse width
3uA(typ) supply current
Guaranteed reset valid to Vdd = +1V
Power supply transient immunity
No external components
Ordering Information
Part No.
TS823CX5
x
TS824CX5
x
TS825CX5
x
Note:
x
is the threshold voltage type, option as
A: 4.63V
B: 4.38V
D: 3.08V
E: 2.93V
F: 2.63V
G: 2.32V
H: 2.19V
- 40 ~ +85 C
o
Operating Temp.
Package
SOT-25
Applications
Computers and Controllers
Embedded Controllers
Intelligent instruments
Critical uP monitoring
Portable / Battery powered equipment
Automotive Systems
Pin Assignment
Function
RESET
(Active-Low)
Ground
Manual Reset
(RESET)
(Active-High)
Watchdog Input
Supply Voltage (Vdd)
TS823
1
2
3
-
4
5
TS824
1
2
-
3
4
5
TS825
1
2
4
3
-
5
TS823/824/825
1-6
2003/12 rev. A
Absolute Maximum Rating
Supply Voltage
Supply Voltage - Recommended
Operating Junction Temperature Range
Storage Temperature Range
Vdd
Vdd
T
OP
T
STG
6.0
0.9 ~ 5
-40 ~ +125
-65 ~ +150
V
V
o
o
C
C
Caution: stress above the listed absolute rating may cause permanent damage to the device
Thermal Information
Thermal Resistance
Maximum Junction Temperature
Maximum Lead Temperature (300
o
C)
Θjc
Tj
T
LEAD
256
150
10
o
C/W
V
S
Electrical Characteristics
Ta = 25
o
C, unless otherwise specified.
Parameter
Input Supply Voltage
Supply Current
Conditions
WDI and MRB unconnected
TS823/824/825CX5A
TS823/824/825CX5B
TS823/824/825CX5D
Symbol
Vdd
Idd
Min
1.0
--
4.56
4.31
3.03
Typ
--
3
4.63
4.38
3.08
2.93
2.63
2.32
2.19
--
--
40
210
1760
--
--
--
-8
8
--
--
--
100
500
--
Max
5.5
10
4.7
4.45
3.13
2.97
2.67
2.36
2.23
0.5
--
--
280
2400
--
0.7
--
0.7
15
0.7
--
--
--
--
120
Unit
V
uA
Reset Threshold
TS823/824/825CX5E
TS823/824/825CX5F
TS823/824/825CX5G
TS823/824/825CX5H
V
TH
2.89
2.59
2.28
2.15
V
RESET Output Voltage Low
(RESET) Output Voltage High
Vdd to Reset Delay
Reset Active Timeout Period
Watchdog Timeout Period
WDI Pulse Width
WDI Input Threshold
Vdd < V
TH(MIN),
I
SINK
=1.2mA,
Vdd > V
TH(MAX),
I
SOURCE
=0.5mA
Vdd = V
TH
- 100mV
Ta = -40
o
C ~ +85
o
C
V
OL
V
OH
T
D1
T
D2
T
WD
T
WDI
--
0.8 Vdd
--
140
1120
50
--
0.8 Vdd
-15
--
--
0.8 Vdd
1
--
V
V
uS
mS
mS
nS
V
V
uA
uA
V
V
uS
nS
nS
KΩ
Vdd = V
TH
x 1.2
WDI
IL
WDI
IH
WDI Input Current
WDI = 0V
WDI = Vdd = 5V
I
IL
I
IH
MR
IL
MR
IH
MR Input Threshold
Vdd = V
TH
x 1.2
MR Pulse Width
MR Noise Immunity
MR to Reset Delay
MR Pull Up Resistance
Pulse width with no reset
Vdd = V
TH
- 100mV
T
WMR
T
DMR
--
80
TS823/824/825
2-6
2003/12 rev. A
Detail Description
Pin Function
**
RESET
RESET is active low.
**
GND
Ground
**
(RESET)
(RESET) is active high.
**
MR
This pin is active low. Pulling this pin low to forces a
reset. After a low to high transition reset remains
asserted for exactly one reset timeout period. This pin
is internally pulled high. If this function is unused then
float this pin or tie it to Vdd.
**
WDI
Watch Dog Input. Any transition on this pin will reset
the Watch Dog timer. If this pin remains high or low for
longer than the Watch Dog interval then a reset is
asserted. Float or tri-state this pin to disable the Watch
Dog feature.
**
Vdd
Positive power supply. A reset is asserted after this
voltage drops below a predetermined level. After Vdd
rises above that level reset remains asserted until the
end of the reset timeout period.
Manual Reset Input
The TS823 and TS825 feature a manual reset feature
(MR). A logic low on the MR pin asserts a reset. The
reset remains asserted a long as the MR pin remains
low. After the MR pin transitions to a high state the reset
remains asserted for the prescribed reset interval (T
D2
).
The MR pin is internally pulled up to Vdd by a 100KΩ
resistor. It is internally de-bounced to reject switching
transients.
The MR pin is ESD protected by diodes connected to
Vdd and Gnd. So the MR pin should never be driven
higher than Vdd or lower than Gnd.
Applications Information
The TS823/824/825 are designed to interface with the
reset input of a microprocessor and to prevent CPU
execution errors due to power up, power down, and
other power supply errors. The TS823/824 also monitor
the CPU health by checking for signal transitions form
the CPU at the WDI input.
Watchdog Input
The TS823 and TS824 are equipped with a watchdog
input (WDI). If the microprocessor does not produce a
valid logic edge at the watchdog input (WDI) within the
prescribed watchdog interval (T
WD
) then a reset asserts.
The reset remains asserted for the required reset
interval (T
D2
). Ata the end of the reset interval the reset
is deasserted and the watchdog interval timer starts
again from zero.
If the watchdog input is left unconnected or is connected
to a tri-stated buffer the watchdog function is disabled.
As soon as the WDI input is driven either low or high the
watchdog function resumes with the watchdog timer set
to zero.
Reset Output
Active low reset outputs are denoted as RESET, Active
high reset output are denoted as (RESET),
A reset will be asserted if any of three things happen:
1) Vdd drops below the threshold (Vth)
2) The MR pin is pulled low.
3) The WDI pin does not detect a transition within the
Watch Dog interval (T
WD
)
The reset will remain asserted for the prescribed reset
interval after:
1) Vdd rises above the threshold (Vth)
2) MR goes high
3) The Watch Dog timer have timed out causing the
reset to assert.
TS823/824/825
3-6
2003/12 rev. A
Detail Description (continued)
Watchdog Input Current
The watchdog input pin (WDI) typically sources/sinks
8uA when driven high or low. So from a power
dissipation point of view the duty cycle of the waveform
at WDI is unimportant. When the WDI pin is floating or
tri-stated the power supply current fall to less than 3uA.
Glitch Rejection
The TS823/824/825 family will reject negative going
transients on the Vdd line to some extent. The smaller
the duration of the transient the larger its amplitude may
be without triggering a reset. The “Glitch Rejection”
chart in the graphs section of this datasheet shows the
relation between glitch amplitude and allowable glitch
duration to avoid unintended resets.
Accurate Output State at Low Vdd
With Vdd voltage on the order of the MOS transistor
threshold (<1V) the outputs of the TS823/824/825 may
become undefined. For parts with active low output
RESET a resistor placed between RESET and Gnd on
the order of 100KΩ will ensure that the RESET output
stays low when Vdd is lower than the threshold voltage
of the part. In a like manner a resistor on the order of
100KΩ when placed between (RESET) and Vdd will
ensure parts with active high output (RESET) will remain
high when Vdd is lower than the threshold voltage of the
parts.
TS823/824/825
4-6
2003/12 rev. A
Electrical Characteristics Curve
TS823/824/825
5-6
2003/12 rev. A
FPGA/CPLD
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