Data Sheet
PT7C4363
Real-time Clock Module (I
2
C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
•
•
•
Using external 32.768kHz quartz crystal
Supports I
2
C-Bus's high speed mode (400 kHz)
Includes time (Hour/Minute/Second) and calendar
(Year/Month/Date/Day) counter functions (BCD
code)
•
•
•
•
Programmable square wave output signal
Oscillator stop flag
Low backup current: typ. 500nA at V
DD
=3.0V and
T
A
=25
°C
Operating range: 1.8V to 5.5V
Description
The PT7C4363 serial real-time clock is a low-power
clock/calendar with a programmable square-wave output.
Address and data are transferred serially via a 2-wire
bidirectional bus. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The date at the end of the month is automatically
adjusted for months with fewer than 31 days, including
corrections for leap year. The clock operates in the 24-
hour format indicator.
Table 1 shows the basic functions of PT7C4363. More
Ordering Information
Part Number
PT7C4363P
PT7C4363W
Package
8-Pin DIP
8-Pin SOIC
details are shown in section: overview of functions.
Note:
Lead free package is available by adding “E” after each
part number. For example: PT7C4363PE.
Table 1.
Basic functions of PT7C4363
Item
Function
Source: Crystal: 32.768kHz
1
Oscillator
Oscillator enable/disable
Oscillator fail detect
Time display
2
Time
Century bit
Time count chain enable/disable
3
4
5
Interrupt
Alarm interrupt
Timer interrupt output
2-wire I
2
C bus
3-wire bus
Burst mode
Write protection
External clock test mode
Power-on reset override
12-hour
24-hour
PT7C4363
√
-
√
-
√
√
√
√
√
1, 32, 1.024k, 32.768k
√
-
-
-
√
√
Programmable square wave output (Hz)
Communicat
ion
6
Control
PT0207(07/05)
1
Ver: 0
Data Sheet
PT7C4363
Real-time Clock Module (I
2
C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Function Block
PT7C4363
X1
32.768
kHz
C
D
Comparator
Alarm Register
(Min, Hour, Day, Date)
OSC
Counter Chain
Timer
Time Counter
(Sec,Min,Hour,Day,Date,Month,Year)
X2
C
G
Control Register
Address
Decoder
Address
Register
I /O
Interface
(I
2
C)
Shift Register
SCL
INT
SQW
Timer / Alarm Interrupt Control
Square Wave Output Control
SDA
Note:
PT7C4363 need to add a 10pF ~ 30pF capacitor between X1 and GND to get the accurate 32k frequency.
Recommended Layout for Crystal
PT7C4363
PT7C4307
X1
32.768kHz
Crystal
X2
Local Ground plane
Layer 2
Guard Ring
(connect to gound)
Crystal Specifications
Parameter
Nominal Frequency
Series Resistance
Load Capacitance
Symbol
f
O
ESR
C
L
Min
Typ
32.768
10
Max
40
Unit
kHz
kΩ
pF
The crystal, traces and crystal input pins should be isolated from RF generating signals.
PT0207(07/05)
2
Ver: 0
Data Sheet
PT7C4363
Real-time Clock Module (I
2
C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pin Configuration
PT7C4363
1
X1
VCC
8
2
X2
INT
SQW
7
SCL
6
3
4
GND
SDA
5
DIP-8
SOIC-8
Pin Description
Pin no.
1
Pin
X1
Type
I
Description
Oscillator Circuit Input.
Together with X2, 32.768kHz crystal is connected between them.
2
X2
O
Oscillator Circuit Output.
Together with X1, 32.768kHz crystal is connected between them.
3
INT
O
Interrupt Output.
Open drain, active low.
4
GND
P
Ground.
Serial Data Input/Output.
SDA is the input/output pin for the 2-wire serial interface. The
SDA pin is open-drain output and requires an external pull-up resistor.
Serial Clock Input.
SCL is used to synchronize data movement on the I
2
C serial interface.
Clock Output.
Open drain. Four frequencies selectable: 32.768k, 1.024k, 32, 1Hz when
SQWE bit is set to 1.
Power.
5
6
7
SDA
SCL
SQW
I/O
I
O
8
VCC
P
PT0207(07/05)
3
Ver: 0
Data Sheet
PT7C4363
Real-time Clock Module (I
2
C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Function Description
Overview of Functions
1.
Clock function
CPU can read or write data including the year (last two digits), month, date, day, hour, minute, and second. Any (two-digit) year
that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2100.
2.
Alarm function
These devices have one alarm system that outputs interrupt signals from INTA for PT7C4363 or INT/OUT/SQW for PT7C4341
to CPU when the date, day of the week, hour, minute or second correspond to the setting. Each of them may output interrupt
signal separately at a specified time. The alarm may be selectable between on and off for matching alarm or repeating alarm.
3.
Programmable square wave output
A square wave output enable bit controls square wave output at pin 7. 4 frequencies are selectable: 1, 32, 1.024k, 32.768k Hz.
4.
Interface with CPU
Data is read and written via the I
2
C bus interface using two signal lines: SCL (clock) and SDA (data).
Since the output of the I/O pin SDA is open drain, a pull-up resistor should be used on the circuit board if the CPU output I/O is
also open drain.
The SCL's maximum clock frequency is 400 kHz, which supports the I
2
C bus's high-speed mode.
5.
Oscillator fail detect
When oscillator fail, OSF bit will be set.
6.
Oscillator enable/disable
Only time count chain can be enable or disable by STOP bit..
7.
Timer function
The timer control register determines one of 4 source clock frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or 1/60 Hz) and
enables or disables the timer. The timer counts down from software loaded 8-bit binary value. At the end of every countdown, the
timer sets the Timer Flag (TF). The TF may only be cleared by software. The asserted TF can be used to generate an interrupt.
The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the
condition of TF. Bit TI/TP is used to control this mode selection. When reading the timer, the current countdown value is returned.
8.
Reset function
The PT7C4363 includes an internal reset circuit which is active whenever the oscillator is stopped. In the reset state the I
2
C-bus
logic is initialized and all registers, including the address pointer, are cleared with the exception of bits FE, OSF, TD1, TD0,
TESTC and AE which are set to logic 1.
PT0207(07/05)
4
Ver: 0
Data Sheet
PT7C4363
Real-time Clock Module (I
2
C Bus)
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Registers
1.
Allocation of registers
Function (time range
BCD format)
Control/status 1
Control/status 2
Seconds (00-59)
Minutes (00-59)
Hours (00-23)
Dates (01-31)
Days of the week (00-06)
Months (01-12)
Years (00-99)
Alarm: Minutes (00-59)
Alarm: Hours (01-12)
Alarm: Dates (01-31)
Alarm: Weekday (00-06)
SQW control
Timer control
Timer
Register definition
Bit 7
TEST1
*
2
Addr.
(hex)
*1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
Bit 6
-
-
S40
M40
×
×
×
×
Y40
M40
×
×
×
×
×
Bit 5
STOP
*3
-
S20
M20
H20
D20
×
×
Y20
M20
H20
D20
×
×
×
Bit 4
-
TI/TP
*5
S10
M10
H10
D10
×
MO10
Y10
M10
H10
D10
×
×
×
Bit 3
TESTC
*4
AF
*6
S8
M8
H8
D8
×
MO8
Y8
M8
H8
D8
×
×
×
Bit 2
-
TF
*6
S4
M4
H4
D4
W4
MO4
Y4
M4
H4
D4
W4
×
×
Bit 1
-
AIE
*7
S2
M2
H2
D2
W2
MO2
Y2
M2
H2
D2
W2
RS1
TD1
*11
Bit 0
-
TIE
*7
S1
M1
H1
D1
W1
MO1
Y1
M1
H1
D1
W1
RS0
TD0
*11
-
OSF
*8
×
×
×
×
Century
Y80
AE
*9
AE
*9
AE
*9
AE
*9
SQWE
TE
*10
Timer count down value
Caution points:
*1. PT7C4363 uses 8 bits for address. For excess 0FH address, PT7C4363 will not respond.
*2. EXT_CLK test mode select bit.
*3. When the bit is logic 1, time count chain stops but oscillator still runs.
*4. Power-on reset override enable bit.
*5. Timer interrupt output select bit.
*6. Alarm and timer interrupt flag bits.
*7. Alarm and timer interrupt enable bits.
*8. Oscillator fail indicates. Indicate clock integrity.
*9. Alarm enable bit. Alarm will be active when related time is matching if AE = 0.
*10. Timer enable bit.
*11. Timer source clock frequency select.
*12. All bits marked with "×" are not implemented. All bits marked with "-" are not used bits and should always be written with
logic 0. If read them, they could be logic 0 or 1.
PT0207(07/05)
5
Ver: 0
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
