IDT74ALVCH162841
3.3V CMOS 20-BIT BUS-INTERFACE D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT
BUS-INTERFACE D-TYPE
LATCH WITH 3-STATE OUT-
PUTS AND BUS-HOLD
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
– V
CC
= 3.3V ± 0.3V, Normal Range
– V
CC
= 2.7V to 3.6V, Extended Range
– V
CC
= 2.5V ± 0.2V
– CMOS power levels (0.4µ W typ. static)
– Rail-to-Rail output swing for increased noise margin
Drive Features for ALVCH162841:
– Balanced Output Drivers: ±12mA
– Low switching noise
–
–
–
IDT74ALVCH162841
ance loads. This device is particularly suitable for implementing buffer
registers, unidirectional bus drivers, and working registers.
The ALVCH162841 can be used as two 10-bit latches or one 20-bit
latch. The 20 latches are transparent D-type latches. The device has
noninverting data (D) inputs and provides true data at its outputs. While
the latch-enable (1LE or 2LE) input is high, the Q outputs of the
corresponding 10-bit latch follow the D inputs. When LE is taken low, the
Q outputs are latched at the levels set up at the D inputs. A buffered
output-enable (1OE or 2OE) input can be used to place the outputs of the
corresponding 10-bit latch in either a normal logic state (high or low logic
levels) or a high-impedance state. In the high-impedance state, the
outputs neither load nor drive the bus lines significantly. OE does not
affect the internal operation of the latches. Old data can be retained or
new data can be entered while the outputs are in the high-impedance
state,
The ALVCH162841 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
The ALVCH162841 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This bus-interface D-type latch is built using advanced dual metal
CMOS technology. The ALVCH162841 features 3-state outputs de-
signed specifically for driving highly capacitive or relatively low-imped-
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
2
OE
28
1
LE
56
2
LE
29
1
D
1
55
1D
2
1
Q
1
2
D
1
42
1D
15
2
Q
1
C1
C1
TO N IN E OTH ER CH AN N ELS
TO N IN E OTH ER CH AN N ELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4693/-
IDT74ALVCH162841
3.3V CMOS 20-BIT BUS-INTERFACE D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OE
1
Q
1
1
Q
2
ABSOLUTE MAXIMUM RATING
56
55
54
53
52
51
50
49
48
47
46
45
1
LE
1
D
1
1
D
2
(1)
Unit
V
V
°C
mA
mA
mA
mA
NEW16link
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
GND
1
Q
3
1
Q
4
GND
1
D
3
1
D
4
Description
Terminal Voltage
with Respect to GND
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to + 4.6
– 0.5 to
V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
V
CC
1
Q
5
1
Q
6
1
Q
7
V
CC
1
D
5
1
D
6
1
D
7
GND
1
Q
8
1
Q
9
1
Q
10
2
Q
1
2
Q
2
2
Q
3
GND
1
D
8
1
D
9
1
D
10
2
D
1
2
D
2
2
D
3
SO56-1 44
SO56-2 43
SO56-3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
GND
2
Q
4
2
Q
5
2
Q
6
GND
2
D
4
2
D
5
2
D
6
CAPACITANCE
(T
A
= +25
o
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
NEW16link
V
CC
2
Q
7
2
Q
8
V
CC
2
D
7
2
D
8
NOTE:
1. As applicable to the device type.
GND
2
Q
9
2
Q
10
2
OE
GND
2
D
9
2
D
10
2
LE
SSOP/TSSOP/TVSOP
TOP VIEW
FUNCTION TABLE
xDx
Inputs
xLE
H
H
L
X
(each 10-bit latch) (1)
xOE
L
L
L
H
Output
xQx
H
L
Q
0
Z
PIN DESCRIPTION
Pin Names
xDx
xLE
xOE
xQx
Description
Data Inputs
(1)
H
L
X
X
Latch Enable Inputs
Output Enable Inputs (Active LOW)
3-State Outputs
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
Q
0
= Level of the indicated steady-state input conditions were established.
NOTE:
1. These pins have “Bus-Hold.” All other pins are standard inputs,
outputs, or I/Os.
2
IDT74ALVCH162841
3.3V CMOS 20-BIT BUS-INTERFACE D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
40
µA
µA
V
mV
µA
µA
V
Unit
V
—
—
750
µA
NEW16link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NEW16link
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2.0V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
± 500
Unit
µA
µA
µA
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74ALVCH162841
3.3V CMOS 20-BIT BUS-INTERFACE D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
(1)
SWITCHING CHARACTERISTICS
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK
(o)
Parameter
Propagation Delay
xDx to xQx
Propagation Delay
xLE to xQx
Output Enable Time
xOE to xQx
Output Disable Time
xOE to xQx
Set-Up Time, data before LE↑
Hold Time, data after LE↑
Pulse Width, xLE HIGH or LOW
Output skew
(2)
Min
.
1.3
1.2
1.2
1.1
0.9
1.1
3.3
—
V
CC
= 2.5V ± 0.2V
Max.
5.5
6
6.7
5.5
—
—
—
—
Min
.
—
—
—
—
0.7
1.4
3.3
—
V
CC
= 2.7V
Max.
5.2
5.6
6.6
5
—
—
—
—
V
CC
= 3.3V ± 0.3V
Min
.
1.3
1.1
1.1
1.2
1.1
1
3.3
—
Max.
4.5
5
5.5
4.6
—
—
—
500
Unit
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
5
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