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LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
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About This Manual
Introduction
This user reference manual includes hardware and software information on the RC32334 (Y revision)
1
,
a high performance integrated processor that combines a high performance 32-bit CPU core with system
logic to provide direct connection to boot memory, main memory, I/O, and PCI. It also includes on-chip
peripherals such as DMA channels, reset circuitry, interrupts, timers, and UARTs.
This is also the user reference manual for the RC32332 (Y revision) integrated processor. The informa-
tion herein generally refers explicitly only to the RC32334 but is applicable to the RC32332 unless noted
otherwise. Differences between the RC32334 and the RC32332 are identified in Appendix G.
Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical character-
istics can be found in the data sheet for this device, which is available from the IDT website
(www.idt.com)
as well as through your local IDT sales representative.
Notes
Content Summary
Chapter 1, “RC32334 Device Overview,”
provides a complete introduction to the performance capabil-
ities of the RC32334. Included in this chapter is a summary of features for the device as well as a system
block diagram and internal register maps.
Chapter 2, “RC32300 CPU Core,”
describes the features of the RC32300 CPU core.
Chapter 3, “CPU Instruction Set Overview,”
presents a general overview on the three CPU instruc-
tion formats as well as the computational instructions of the MIPS architecture. Instruction set summary
tables are also provided.
Chapter 4, “CPU Pipeline Architecture,”
discusses pipeline features as well as interlock and excep-
tion handling of the device’s RISCore™ 32300.
Chapter 5, “Memory Management,”
contains a discussion on the virtual-to-physical address transla-
tion technique, TLB management, and operation modes for the RC32334. Register formats and field
description tables are also provided in this chapter.
Chapter 6, “CPU Exception Processing,”
defines and describes the various exception types and
handling processes for the RC32334. Also provided in this chapter are the CPO register formats, their field
descriptions, and general exception handling flowcharts.
Chapter 7, “Cache Organization, Operation, and Coherency,”
includes a general discussion on the
operation of cache as well as the more specific cache attributes of the RC32334. Flowcharts and various
diagrams are provided to clarify the concepts discussed in this chapter.
Chapter 8, “RC32334 Internal Bus,”
presents a general overview of the RC32334’s internal bus that
provides a connection to internal peripherals and controllers.
Chapter 9, “External Local Bus Interface,”
presents a general overview of the RC32334’s system bus
that provides an easy connection to main memory and to peripherals.
Chapter 10, “Memory Controller,”
provides a functional overview on the CPU core, DMA or PCI bridge
generated transactions. A block diagram, register maps, signal description table, and timing diagrams for
various read and write operations are also included.
1.
For information on an earlier user manual that covers the Z revision, contact your IDT sales representative.
i
June 4, 2002
79RC32334/332 User Reference Manual
About This Manual
Content Summary
Notes
Chapter 11, “Synchronous DRAM Controller,”
contains a discussion on the operations and support
provided by the RC32334’s 32-bit SDRAM controller. Timing diagrams are provided to illustrate the different
read and write transactions.
Chapter 12, “PCI Interface Controller,”
contains descriptions of the PCI host/satellite modes and
master/target operations supported in the RC32334. Register maps and register field definitions are
included.
Chapter 13, “DMA Controllers,”
includes descriptions on the four general purpose DMA channels and
the transfer operations supported. Byte swapping between big- and little-endian is also discussed and
includes examples.
Chapter 14, “Expansion Interrupt Controller,”
provides a functional and operational overview on this
controller. This chapter includes a block diagram, signal definitions and register mapping tables for each of
the 14 groups supported.
Chapter 15, “Programmable I/O (PIO) Controller,”
provides the signal descriptions, register mapping
and programming information on the software programmable options of the RC32334’s 15 peripheral pins.
Chapter 16, “Timer Controller,”
provides a user overview on the functions of the RC32334’s nine on-
chip timers. A block diagram, signal definitions and register maps are included.
Chapter 17, “UART Controller,”
describes the operation of the two 16550 compatible UARTs available
on the RC32334. Register maps and descriptions are included.
Chapter 18, “Serial Peripheral Interface,”
describes the properties and operations of this interface to
low-cost serial peripherals.
Chapter 19, “Clocking, Reset, and Initialization,”
provides a description of the clock signals that are
used on the RC32334 processor and includes a discussion on the basic system clocks and system timing
parameters. This chapter also provides a brief explanation on the power reduction modes for this device
and a description of the RC32334 initialization and reset registers.
Chapter 20, “JTAG Boundary Scan,”
introduces the standard JTAG interface used for board-level
debugging. A description on the Test Access Port (TAP) interface and TAP controller state assignments is
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