TSA1201
12-BIT, 50MSPS, 150mW A/D CONVERTER
s
0.5Msps to 50Msps sampling frequency
s
40mW @5Msps, 150mW @ 50Msps
s
2.5V supply voltage with 2.5V/3.3V compati-
s
s
s
s
s
bility for digital I/O
Input range: 2Vpp differential
SFDR up to 77dB @ 50Msps, Fin=15MHz
ENOB up to10.5 bits @ 50Msps, Fin=15MHz
Built-in reference voltage with external bias
capability
Pinout compatibility with TSA0801, TSA1001
and TSA1002
ORDER CODE
Part Number
TSA1201IF
TSA1201IFT
EVAL1201/AA
Temperature
Range
-40°C to +85°C
-40°C to +85°C
Package
TQFP48
TQFP48
Conditioning
Tray
Tape & Reel
Marking
SA1201I
SA1201I
Evaluation board
PIN CONNECTIONS
(top view)
DESCRIPTION
GNDBE
VCCBE
VCCBI
AVCC
AGND
The TSA1201 is a 12-bit, 50MHz maximum
sampling frequency Analog to Digital converter
using a CMOS technology combining high
performances and very low power consumption.
The TSA1201 is based on a pipeline structure and
digital error correction to provide excellent static
linearity and achieve 10.5 effective bits at
Fs=50Msps, and Fin=15MHz, with a global power
consumption of 150mW.
The TSA1201 features adaptative behaviour to
the application. Its architecture allows to sample
from 0.5Msps up to 50Msps, with a programmable
power consumption which makes the application
board even more optimized.
It integrates a proprietary track-and-hold structure
to ensure an high analog bandwidth of 1GHz and
enable IF-sampling.
Several features are available on the device. A
voltage reference is integrated in the circuit.
Differential or single-ended analog inputs can be
applied. The output data can be coded into two
differential formats. A Data Ready signal is raised
as the data is valid on the output and can be used
for synchronization purposes.
The TSA1201 is available in extended (-40°C to
+85°C) temperature range, in small 48 pins TQFP
package.
APPLICATIONS
AVCC
DFSB
OEB
SRC
NC
NC
DR
index
corner
48
IPOL
VREFP
VREFM
AGND
VIN
AGND
VINB
AGND
INCM
1
2
3
4
5
6
7
8
9
47 46
45
44 43
42
41
40
39
38 37
36 NC
35 D0 (LSB)
34 D1
33 D2
32 D3
31 D4
TSA1201
30 D5
29 D6
28 D7
27 D8
26 D9
25 D10
AGND 10
AVCC 11
AVCC 12
13
14 15
16
17
18 19
20
21
22
23
24
DVCC
DVCC
DGND
CLK
DGND
NC
DGND
GNDBI
GNDBE
VCCBE
OR
D11 (MSB)
PACKAGE
7 x 7 mm TQFP48
s
s
s
s
s
High speed data acquisition
Medical imaging and ultrasound
Portable instrumentation
High speed DSP interface
Digital communication - IF sampling
1/20
March 2001
TSA1201
ABSOLUTE MAXIMUM RATINGS
Symbol
AVCC
DVCC
VCCBI
VCCBE
Tstg
ESD
Analog Supply voltage
1)
Digital Supply voltage
1)
Digital buffer Supply voltage
1)
Digital buffer Supply voltage
1)
Storage temperature
Electrical Static Discharge
- HBM
- CDM-JEDEC Standard
Parameter
Values
0 to 3.3
0 to 3.3
0 to 3.3
0 to 3.6
+150
2
1.5
Unit
V
V
V
V
°C
KV
1. All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages
must never exceed -0.3V or VCC+0V
OPERATING CONDITIONS
Symbol
AVCC
DVCC
VCCBI
VCCBE
VREFP
VREFM
Parameter
Analog Supply voltage
Digital Supply voltage
Internal (quiet) buffer Supply voltage
External (noisy) buffer Supply voltage
Forced top voltage reference
Bottom internal reference voltage input
Test conditions
Min
2.25
2.25
2.25
2.25
0.8
0
Typ
2.5
2.5
2.5
2.5
-
Max
2.7
2.7
2.7
3.5
AVCC
1
Unit
V
V
V
V
V
V
BLOCK DIAGRAM
+2.5V +2.5V/3.3V
VREFP
GNDA
VIN
INCM
VINB
stage
1
stage
2
stage
n
Reference
circuit
IPOL
VREFM
DFSB
Sequencer-phase shifting
CLK
SRC
OEB
Timing
Digital data correction
DR
DO
TO
D11
OR
GND
Buffers
2/20
TSA1201
PIN CONNECTIONS
(top view)
GNDBE
VCCBE
VCCBI
AVCC
AGND
AVCC
DFSB
OEB
SRC
DR
NC
NC
index
corner
48
IPOL
VREFP
VREFM
AGND
VIN
AGND
VINB
AGND
INCM
AGND
AVCC
AVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
47 46
45
44 43
42
41
40
39
38 37
36 NC
35 D0 (LSB)
34 D1
33 D2
32 D3
31 D4
TSA1201
30 D5
29 D6
28 D7
27 D8
26 D9
25 D10
14 15
16
17
18 19
20
21
22
23
24
DVCC
DVCC
DGND
CLK
DGND
NC
DGND
GNDBI
VCCBE
OR
D11 (MSB)
GNDBE
PIN DESCRIPTION
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
IPOL
VREFP
VREFM
AGND
VIN
AGND
VINB
AGND
INCM
AGND
AVCC
AVCC
DVCC
DVCC
DGND
CLK
DGND
NC
DGND
GNDBI
GNDBE
VCCBE
OR
Description
Analog bias current input
Top voltage reference
Bottom voltage reference
Analog ground
Analog input
Analog ground
Inverted analog input
Analog ground
Input common mode
Analog ground
Analog power supply
Analog power supply
Digital power supply
Digital power supply
Digital ground
Clock input
Digital ground
Non connected
Digital ground
Digital buffer ground
Digital buffer ground
Digital buffer power supply
Out Of Range output
0V
0V
0V
2.5V/3.3V
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
1V
0V
0V
1Vpp
0V
1Vpp
0V
0.5V
0V
2.5V
2.5V
2.5V
2.5V
0V
2.5V compatible CMOS input
0V
Observation
Pin No
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0(LSB)
NC
NC
DR
VCCBE
GNDBE
VCCBI
NC
SRC
OEB
DFSB
AVCC
AVCC
AGND
Description
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Least Significant Bit output
Non connected
Non connected
Data Ready output
Digital Buffer power supply
Digital Buffer ground
Digital Buffer power supply
Non connected
Slew rate control input
Output Enable input
Data Format Select input
Analog power supply
Analog power supply
Analog ground
2.5V/3.3V CMOS input
2.5V/3.3V CMOS input
2.5V/3.3V CMOS input
2.5V
2.5V
0V
CMOS output (2.5V/3.3V)
2.5V/3.3V
0V
2.5V
Observation
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
D11(MSB) Most Significant Bit output
3/20
TSA1201
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFM=0V
Tamb = 25°C (unless otherwise specified)
TIMING CHARACTERISTICS
Symbol
FS
DC
TC1
TC2
Tod
Tpd
Ton
Toff
Parameter
Sampling Frequency
Clock Duty Cycle
Clock pulse width (high)
Clock pulse width (low)
Data Output Delay (Fall of Clock 6pF load capacitance
to Data Valid)
Data Pipeline delay
Falling edge of OEB to digital
output valid data
Rising edge of OEB to digital
output tri-state
Test conditions
Min
0.5
45
9
9
50
10
10
8
5.5
1
1
Typ
Max
50
55
Unit
MHz
%
ns
ns
ns
cycles
ns
ns
TIMING DIAGRAM
N+2
N+1
N+3
N+4
N
N-3
N-2
N-1
N+5
N+6
CLK
Tpd + Tod
OEB
Tod
Toff
N-9
N-8
N-7
N-6
N-5
N-4
N-3
Ton
N-1
N
DATA
OUT
DR
HZ state
4/20
TSA1201
CONDITIONS
AVCC = DVCC = VCCBE = VCCBI = 2.5V,Fs= 50Msps,Fin=2MHz, Vin@ -1dBFS, VREFM=0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
Symbol
Parameter
Test conditions
Min
Typ
2.0
7.0
5
Vin@Full Scale, Fs=50Msps
1000
90
Max
Unit
Vpp
pF
MΩ
MHz
MHz
VIN-VINB Full scale reference voltage
Cin
Rin
BW
ERB
Input capacitance
Differential input resistance
Analog Input Bandwitdh
Effective Resolution Bandwidth
1)
1. See parameters definition for more information.
REFERENCE VOLTAGE
Symbol
VREFP
Parameter
Top internal reference voltage
Test conditions
Min
0.79
Tmin= -40°C to Tmax= 85°C
1)
0.79
1.08
Vpol
Analog bias voltage
Tmin= -40°C to Tmax= 85°C
1)
1.07
0.40
VINCM
Input common mode voltage
Tmin= -40°C to Tmax= 85°C
1)
0.4
0.55
1.15
Typ
1.0
Max
1.16
1.16
1.22
1.23
0.65
0.65
Unit
V
V
V
V
V
V
1. Not fully tested over the temperature range. Guaranted by sampling.
5/20
FPGA/CPLD
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