TSA1203
DUAL-CHANNEL, 12-BIT, 40MSPS, 230mW A/D CONVERTER
s
Low power consumption: 230mW@40Msps
s
Single supply voltage: 2.5V
s
s
s
s
s
s
Independent supply for CMOS output stage
with 2.5V/3.3V capability
SFDR= -68.3 dBc @ Fin=10MHz
1GHz analog bandwidth Track-and-Hold
Common clocking between channels
Dual simultaneous Sample and Hold inputs
Multiplexed outputs
Built-in reference voltage with external bias
capability
PIN CONNECTIONS
(top view)
GNDBE
D0(LSB)
VCCBE
REFPI
VCCBI
REFMI
VCCBI
INCMI
AVCC
AVCC
OEB
D1
index
corner
48 47 46 45
AGND 1
INI
2
44 43 42
41 40 39 38 37
36 D2
35 D3
34 D4
33 D5
32 D6
31 D7
AGND 3
INIB 4
AGND 5
IPOL 6
AVCCB 7
AGND 8
INQ 9
AGND 10
INBQ 11
AGND 12
13
14 15 16
17 18 19 20 21 22 23 24
TSA1203
30 D8
29 D9
28 D10
27 D11(MSB)
26 VCCBE
25 GNDBE
DESCRIPTION
The TSA1203 is a new generation of high speed,
dual-channel Analog to Digital converter pro-
cessed in a mainstream 0.25µm CMOS technolo-
gy yielding high performances and very low power
consumption.
The TSA1203 is specifically designed for applica-
tions requiring very low noise floor, high SFDR
and good isolation between channels. It is based
on a pipeline structure and digital error correction
to provide high static linearity at Fs=40Msps, and
Fin=10MHz.
For each channel, a voltage reference is integrat-
ed to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC outputs are multiplexed in a common
bus with small number of pins. A tri-state capabili-
ty is available for the outputs, allowing chip selec-
tion. The inputs of the ADC must be differentially
driven.
The TSA1203 is available in extended (0 to
+85°C) temperature range, in a small 48 pins
TQFP package.
APPLICATIONS
BLOCK DIAGRAM
+2.5V/3.3V
CLK
SELECT
OEB
REFPQ
REFMQ
INCMQ
AGND
AVCC
DVCC
Timing
VINI
VINBI
VINCMI
VREFPI
VREFMI
IPOL
VREFPQ
VREFMQ
VINCMQ
VINQ
VINBQ
REF Q
AD 12
I channel
12
DGND
CLK
SELECT
DGND
DVCC
GNDBI
VCCBE
common mode
REF I
Polar.
M
U
X
12
12
Buffers
D0
TO
D11
common mode
AD 12
Q channel
12
s
s
s
s
s
Medical imaging and ultrasound
3G basestation
I/Q signal processing applications
High speed data acquisition system
Portable instrumentation
GND
GNDBE
PACKAGE
ORDER CODE
Part Number
TSA1203IF
TSA1203IFT
EVAL1203/BA
Temperature
Range
0°C to +85°C
0°C to +85°C
Package
TQFP48
TQFP48
Conditioning
Tray
Tape & Reel
Marking
SA1203I
SA1203I
7
×
7 mm TQFP48
Evaluation board
February 2003
1/20
TSA1203
CONDITIONS
AVCC = DVCC = VCCB = 2.5V, Fs= 40Msps, Fin=10.13MHz, Vin@ -1dBFS, VREFP=0.8V, VREFM=0V
Tamb = 25°C (unless otherwise specified)
DYNAMIC CHARACTERISTICS
Symbol
SFDR
SNR
THD
SINAD
ENOB
Parameter
Spurious Free Dynamic Range
Signal to Noise Ratio
Total Harmonics Distortion
Signal to Noise and Distortion Ratio
Effective Number of Bits
56.5
9.1
60.7
Test conditions
Min
Typ
-68.3
66.1
-66.6
62.8
10.3
-58
Max
-59.5
Unit
dBc
dB
dBc
dB
bits
TIMING CHARACTERISTICS
Symbol
FS
DC
TC1
TC2
Tod
Tpd I
Tpd Q
Ton
Toff
Parameter
Sampling Frequency
Clock Duty Cycle
Clock pulse width (high)
Clock pulse width (low)
Data Output Delay (Clock edge to Data Valid)
Data Pipeline delay for I channel
Data Pipeline delay for Q channel
Falling edge of OEB to digital output valid data
Rising edge of OEB to digital output tri-state
10pF load capacitance
Test conditions
Min
0.5
45
22.5
22.5
50
25
25
9
7
7.5
1
1
Typ
Max
40
55
Unit
MHz
%
ns
ns
ns
cycles
cycles
ns
ns
2/20
TSA1203
TIMING DIAGRAM
Simultaneous sampling
on I/Q channels
N+3
N+4
N+5
N+6
N+12
N+13
I
N+2
N-1
N
Q
N+1
N+7
N+8
N+9
N+10
N+11
CLK
Tpd I + Tod
Tod
SELECT
CLOCK AND SELECT CONNECTED TOGETHER
OEB
sample N-8
I channel
sample N-6
Q channel
sample N
Q channel
sample N+1
Q channel
sample N+2
Q channel
DATA
OUTPUT
sample N-9
I channel
sample N-7
Q channel
sample N+1 sample N+2
I channel
I channel
sample N+3
I channel
PIN CONNECTIONS
(top view)
GNDBE
D0(LSB)
VCCBE
REFPI
VCCBI
REFMI
VCCBI
INCMI
AVCC
AVCC
OEB
D1
index
corner
48
AGND 1
INI
2
47 46 45
44 43 42
41 40 39 38 37
36 D2
35 D3
34 D4
33 D5
32 D6
31 D7
AGND 3
INIB 4
AGND 5
IPOL 6
AVCCB 7
AGND 8
INQ 9
AGND 10
INBQ 11
AGND 12
13
14 15 16
17 18 19 20 21 22
23 24
TSA1203
30 D8
29 D9
28 D10
27 D11(MSB)
26 VCCBE
25 GNDBE
REFPQ
REFMQ
INCMQ
AGND
AVCC
DVCC
DGND
CLK
SELECT
DGND
DVCC
GNDBI
3/20
TSA1203
PIN DESCRIPTION
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
AGND
INI
AGND
INBI
AGND
IPOL
AVCC
AGND
INQ
AGND
INBQ
AGND
REFPQ
REFMQ
INCMQ
AGND
AVCC
DVCC
DGND
CLK
SELECT
DGND
DVCC
GNDBI
Description
Analog ground
I channel analog input
Analog ground
I channel inverted analog input
Analog ground
Analog bias current input
Analog power supply
Analog ground
Q channel analog input
Analog ground
Q channel inverted analog input
Analog ground
Q channel top reference voltage
Q channel bottom reference
voltage
Q channel input common mode
Analog ground
Analog power supply
Digital power supply
Digital ground
Clock input
Channel selection
Digital ground
Digital power supply
Digital buffer ground
0V
2.5V
2.5V
0V
2.5V CMOS input
2.5V CMOS input
0V
2.5V
0V
0V
0V
0V
2.5V
0V
0V
0V
0V
Observation
Pin No
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
GNDBE
VCCBE
Description
Digital buffer ground
Digital Buffer power supply
0V
2.5V/3.3V
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
CMOS output (2.5V/3.3V)
2.5V/3.3V - See Application
Note
0V
2.5V
2.5V
2.5V/3.3V CMOS input
2.5V
2.5V
Observation
D11(MSB) Most Significant Bit output
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0(LSB)
VCCBE
GNDBE
VCCBI
VCCBI
OEB
AVCC
AVCC
INCMI
REFMI
REFPI
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Least Significant Bit output
Digital Buffer power supply
Digital buffer ground
Digital Buffer power supply
Digital Buffer power supply
Output Enable input
Analog power supply
Analog power supply
I channel input common mode
I channel bottom reference voltage 0V
I channel top reference voltage
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Symbol
AVCC
DVCC
VCCBE
VCCBI
IDout
Tstg
ESD
Analog Supply voltage
1)
Digital Supply voltage
1)
Digital buffer Supply voltage
1)
Digital buffer Supply voltage
1)
Digital output current
Storage temperature
HBM: Human Body Model
2)
CDM: Charged Device
Latch-up Class
4)
2). ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5kΩ
3). Discharge to Ground of a device that has been previously charged.
4). Corporate ST Microelectronics procedure number 0018695
Parameter
Values
0 to 3.3
0 to 3.3
0 to 3.6
0 to 3.3
-100 to 100
+150
2
1.5
A
Unit
V
V
V
V
mA
°C
kV
Model
3)
1). All voltages values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC
4/20
TSA1203
OPERATING CONDITIONS
Symbol
AVCC
DVCC
VCCBE
VCCBI
VREFPI
VREFPQ
VREFMI
VREFMQ
INCMI
INCMQ
Forced input common mode voltage
0.2
1
V
Parameter
Analog Supply voltage
Digital Supply voltage
External Digital buffer Supply voltage
Internal Digital buffer Supply voltage
Forced top voltage reference
Min
2.25
2.25
2.25
2.25
0.94
Typ
2.5
2.5
2.5
2.5
Max
2.7
2.7
3.5
2.7
1.4
Unit
V
V
V
V
V
Forced bottom reference voltage
0
0.4
V
ANALOG INPUTS
Symbol
Parameter
Test conditions
Differential inputs mandatory
Min
1.1
Typ
2.0
7.0
10
Vin@Full Scale, Fs=40Msps
1000
70
Max
2.8
Unit
Vpp
pF
KΩ
MHz
MHz
VIN-VINB Full scale reference voltage
Cin
Req
BW
ERB
Input capacitance
Equivalent input resistor
Analog Input Bandwidth
Effective Resolution Bandwidth
DIGITAL INPUTS AND OUTPUTS
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
Clock and Select inputs
VIL
VIH
OEB input
VIL
VIH
Logic "0" voltage
Logic "1" voltage
0
0.75 x
VCCBE
VCCBE
0.25 x
VCCBE
V
V
Logic "0" voltage
Logic "1" voltage
2.0
0
2.5
0.8
V
V
Digital Outputs
VOL
VOH
IOZ
C
L
Logic "0" voltage
Logic "1" voltage
Iol=10µA
Ioh=10µA
0
0.9 x
VCCBE
VCCBE
-1.67
0
1.67
15
0.1 x
VCCBE
V
V
µA
pF
High Impedance leakage current OEB set to VIH
Output Load Capacitance
5/20
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