TSA1204
Dual channel 12-bit 20Msps 120mW A/D converter
Features
■
■
■
■
■
■
■
■
■
■
■
0.5 Msps to 20 Msps sampling frequency
Adaptive power consumption: 120 mW @
20 Msps, 95 mW@10 Msps
Single supply voltage: 2.5 V
Independent supply for CMOS output stage
with 2.5 V/3.3 V capability
ENOB=11.2 @ Nyquist
SFDR= -81.5 dBc @ Nyquist
1GHz analog bandwidth track-and-hold
Common clocking between channels
Dual simultaneous sample and hold inputs
Multiplexed outputs
Built-in reference voltage with external bias
capability.
AGND 1
INI
2
AGND 3
INIB 4
REFPI
VCCBI
REFMI
CLKD
VCCBI
7x7mm TQFP48
index
corner
48
47 46 45
44 43 42
Description
The TSA1204 is a new generation of high speed,
dual-channel analog-to-digital converters
implemented in a mainstream 0.25 µm CMOS
technology yielding high performance and very
low power consumption.
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The TSA1204 is specifically designed for
applications requiring very low noise floor, high
SFDR and good insulation between channels. It is
based on a pipeline structure and digital error
correction to provide excellent static linearity and
over 11.2 effective bits at F
S
=20 Msps, and
F
in
=10 MHz.
For each channel, an integrated voltage reference
simplifies the design and minimizes external
components. It is nevertheless possible to use the
circuit with external references.
The ADC outputs are multiplexed in a common
bus with a small number of pins. A tri-state
capability is available for the outputs, allowing
chip selection.
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IPOL 6
AVCCB 7
AGND 8
INQ 9
AGND 10
INBQ 11
AGND 12
AGND 5
te
le
13
REFPQ
14 15 16
REFMQ
INCMQ
AGND
ro
P
41 40 39 38 37
36 D2
35 D3
34 D4
33 D5
32 D6
31 D7
30 D8
29 D9
28 D10
27 D11(MSB)
26 VCCBE
25 GNDBE
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GNDBE
D0(LSB)
VCCBE
D1
s)
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The inputs of the ADC must be differentially
driven.
The TSA1204 is available in extended (-40° C to
+85° C) temperature range, in a small 48-pin
TQFP package.
Applications
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■
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Medical imaging and ultrasound
3G base station
I/Q signal processing applications
High speed data acquisition system
Portable instrumentation
INCMI
AVCC
TSA1204
17 18 19 20 21 22
AVCC
DVCC
DGND
CLK
SELECT
DGND
AVCC
OEB
23 24
DVCC
GNDBI
December 2006
Rev 4
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31
Contents
TSA1204
Contents
1
2
3
4
5
6
7
8
Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.1
Additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.1.1
8.1.2
Output enable mode (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Select mode (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.2
References and common mode connection . . . . . . . . . . . . . . . . . . . . . . . 16
8.2.1
8.2.2
8.3
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8.7.1
8.7.2
8.7.3
8.7.4
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Internal reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16
External reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . 16
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Driving the differential analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EVAL1204/BA evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Evaluation board operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Consumption adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Single and differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.5
8.6
8.7
9
Practical application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.1
9.2
Digital interface applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Medical imaging application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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TSA1204
Contents
10
Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
11
12
13
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Schematic diagram
TSA1204
1
Schematic diagram
Figure 1.
TSA1204 block diagram
+2.5V/3.3V
CLK
SELECT
OEB
VCCBE
Timing
VINI
VINBI
VINCMI
VREFPI
VREFMI
IPOL
VREFPQ
VREFMQ
VINCMQ
VINQ
VINBQ
Polar.
REF Q
AD 12
I channel
12
common mode
REF I
M
U
X
12
12
Buffers
common mode
AD 12
Q channel
Figure 2.
Timing diagram
Simultaneous sampling
on I/Q channels
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I
N-1
Q
CLK
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N
N+1
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t(
N+3
N+2
O
-
N+4
so
b
GND
N+5
N+6
12
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D0
TO
D11
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t(
GNDBE
N+13
N+12
N+7
N+8
N+9
N+10
N+11
Tpd I + Tod
Tod
SELECT
CLOCK AND SELECT CONNECTED TOGETHER
OEB
sample N-8
I channel
sample N-6
Q channel
sample N
Q channel
sample N+1
Q channel
sample N+2
Q channel
DATA
OUTPUT
sample N-9
I channel
sample N-7
Q channel
sample N+1 sample N+2
I channel
I channel
sample N+3
I channel
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TSA1204
Pin descriptions
2
Pin descriptions
Table 1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin descriptions (TQFP48 package)
Description
Analog ground
I channel analog input
Analog ground
I channel inverted
analog input
Analog ground
Analog bias current
input
Analog power supply
Analog ground
Q channel analog
input
Analog ground
Q channel inverted
analog input
Analog ground
0V
2.5 V
0V
0V
0V
Name
AGND
INI
AGND
INBI
AGND
IPOL
AVCC
AGND
INQ
AGND
INBQ
AGND
REFPQ
REFMQ
INCMQ
AGND
AVCC
DVCC
DGND
CLK
SELECT
DGND
DVCC
GNDBI
Observation
0V
Pin
25
26
27
28
29
30
31
32
33
Name
GNDBE
VCCBE
D11(MSB)
D10
D9
D8
D7
D6
Description
Digital buffer ground
Digital Buffer power
supply
Most Significant Bit
output
Digital output
Digital output
Digital output
Observation
0V
2.5 V/3.3 V
CMOS output
(2.5 V/3.3 V)
CMOS output
(2.5 V/3.3 V)
CMOS output
(2.5 V/3.3 V)
CMOS output
(2.5 V/3.3 V)
Digital output
Digital output
Digital output
Q channel top
reference voltage
15
b
O
et
l
so
16
17
18
ro
P
e
Q channel bottom
reference voltage
Q channel input
common mode
Analog ground
Analog power supply
Digital power supply
Digital ground
Clock input
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O
-
0V
0V
so
b
34
35
36
37
38
39
te
le
D5
D4
D3
D2
D1
D0(LSB)
VCCBE
GNDBE
VCCBI
CLKD
OEB
AVCC
AVCC
INCMI
REFMI
REFPI
r
P
d
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t(
CMOS output
(2.5 V/3.3 V)
CMOS output
(2.5 V/3.3 V)
CMOS output
(2.5 V/3.3 V)
CMOS output
(2.5 V/3.3 V)
CMOS output
(2.5 V/3.3 V)
CMOS output
(2.5 V/3.3 V)
CMOS output
(2.5 V/3.3 V)
CMOS output
(2.5 V/3.3 V)
2.5 V/3.3 V - See
Application Note
0V
2.5 V
Idle at high level
2.5 V or 3.3 V
2.5 V/3.3 V CMOS
input
2.5 V
2.5 V
Digital output
Digital output
Digital output
Digital output
Least Significant Bit
output
Digital Buffer power
supply
Digital buffer ground
Digital Buffer power
supply
Data clock input
Output Enable input
Analog power supply
Analog power supply
I channel input
common mode
I channel bottom
reference voltage
I channel top
reference voltage
0V
2.5 V
2.5 V
0V
2.5 V CMOS
input
2.5 V CMOS
input
0V
2.5 V
0V
40
41
42
43
44
45
46
47
48
19
20
21
22
23
24
Channel selection
Digital ground
Digital power supply
Digital buffer ground
0V
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