INTEGRATED CIRCUITS
DATA SHEET
TSA5055T
2.65 GHz bidirectional I
2
C-bus
controlled synthesizer
Product specification
Supersedes data of November 1991
File under Integrated Circuits, IC02
1999 Aug 11
Philips Semiconductors
Product specification
2.65 GHz bidirectional I
2
C-bus controlled
synthesizer
FEATURES
•
Complete 2.65 GHz single-chip system
•
Low power 5 V, 60 mA
•
I
2
C-bus programming
•
In-lock flag
•
Varicap drive disable
•
Low radiation
•
5-level Analog to Digital Converter (ADC)
•
Address selection for Picture-In-Picture (PIP),
DBS tuner, etc.
•
6 controllable outputs, 4 bidirectional
•
Power-down flag
•
Available in SOT109-1 (SO16) package
•
Symmetrical or asymmetrical drive.
APPLICATIONS
•
Satellite TV
•
High IF cable tuning systems.
QUICK REFERENCE DATA
SYMBOL
V
CC
I
CC
f
RF
V
I (rms)
supply voltage
supply current
RF input frequency range
input voltage level (RMS value)
1 to 1.8 GHz
1.8 to 2.65 GHz
f
XTAL
z
XTAL
I
O
T
amb
T
stg
crystal oscillator frequency
crystal oscillator impedance (absolute value)
open-collector output current P7, P6, P5 and P4
output current P3 and P0
ambient temperature
storage temperature
50
70
3.2
600
−
−
−20
−40
−
−
4
1000
−
1
−
−
300
300
PARAMETER
−
1
MIN.
4.5
5
60
−
TYP.
GENERAL DESCRIPTION
TSA5055T
The TSA5055T is a single-chip PLL frequency synthesizer
designed for satellite TV tuning systems. It may be used
with a symmetrical input (pins 13 and 14) or with an
asymmetrical input (pin 13).
Control data is entered via the I
2
C-bus; five serial bytes are
required to address the device, select the oscillator
frequency, program the six output ports and set the
charge-pump current. Four of these ports can also be used
as input ports (three general purpose I/O ports, one ADC).
Digital information concerning these ports can be read out
of the TSA5055T on the SDA line (one status byte) during
a READ operation. A flag is set when the loop is ‘in-lock’
and is read during a READ operation. The device has one
fixed I
2
C-bus address and three programmable
addresses, programmed by applying a specific voltage to
port 3. The phase comparator operates at 7.8125 kHz
when a 4 MHz crystal is used.
MAX.
5.5
80
2.65
V
UNIT
mA
GHz
mV
mV
MHz
Ω
mA
mA
°C
°C
4.48
−
10
−
+85
+150
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TSA5055T
SO16
DESCRIPTION
plastic small outline package; 16 leads; body width 3.9 mm
CODE
SOT109-1
1999 Aug 11
2
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handbook, full pagewidth
1999 Aug 11
1
PD
UD
fDIV
16
CHARGE-
PUMP
15-BIT
PROGRAMMABLE
DIVIDER
TO
CP
7.8125 kHz
fREF
DIVIDER
N = 512
DIGITAL
PHASE
COMPARATOR
IN-LOCK
DETECTOR
LOGIC
15-BIT LATCH
DIVIDER RATIO
BLOCK DIAGRAM
Philips Semiconductors
RFIN1
13
RFIN2
14
PRESCALER
16
Q1 2
Q2 3
OSCILLATOR
4 MHz
POWER DOWN
DETECTOR
TSA5055T
OS
2.65 GHz bidirectional I
2
C-bus controlled
synthesizer
3
3
TTL LEVEL
COMPARATORS
7-BIT LATCH
PORT INFORMATION
GATE
T1
11
P0
P3
P4
10
9
8
P5
7
P6
6
P7
SCL
5
SDA
4
I
2
C-BUS
TRANSCEIVER
15
GND
ADDRESS
SELECTION
3-BIT
ADC
LATCH 3
CONTROL DATA
12
VCC
MBC307
Product specification
TSA5055T
Fig.1 Block diagram.
Philips Semiconductors
Product specification
2.65 GHz bidirectional I
2
C-bus controlled
synthesizer
PINNING
SYMBOL
PD
Q1
Q2
SDA
SCL
P7
P6
P5
P4
P3
P0
V
CC
RF
IN1
RF
IN2
GND
UD
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DESCRIPTION
charge-pump output
crystal oscillator input 1
crystal oscillator input 2
serial data input/output
serial clock input
port output/input (general
purpose)
port output/input (ADC)
port output/input (general
purpose)
port output/input (general
purpose)
port output (also used for address
selection)
port output
voltage supply
RF signal input 1
RF signal input 2 (decoupled)
ground
drive output
handbook, halfpage
TSA5055T
PD 1
Q1 2
Q2 3
SDA 4
16 UD
15 GND
14 RFIN2
TSA5055T
SCL 5
P7 6
P6 7
P5 8
MBC304
13 RFIN1
12 VCC
11 P0
10 P3
9 P4
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
General
The TSA5055T is controlled via the 2-wire I
2
C-bus. For
programming, there is one (7-bit) module address and the
R/W bit for selecting READ or WRITE mode.
WRITE mode: R/W = 0;
see Table 1
After the address transmission (first byte), data bytes can
be sent to the device. Four data bytes are needed to fully
program the TSA5055T. The bus transceiver has an
auto-increment facility that permits the programming of the
TSA5055T within one single transmission (address + four
data bytes).
The TSA5055T can also be partly programmed on the
condition that the first data byte following the address is
byte 2 or byte 4.
The meaning of the bits in the data bytes is given in
Table 1. The first bit of the first data byte transmitted
indicates whether frequency data (first bit = 0) or
charge-pump and port information (first bit = 1) will follow.
Until an I
2
C-bus STOP condition is sent by the controller,
additional data bytes can be entered without the need to
re-address the device. This allows a smooth frequency
sweep for fine tuning. At power-on, the ports are set to the
high-impedance state.
The 7.8125 kHz reference frequency is obtained by
dividing the output of the 4 MHz crystal oscillator by 512.
Because the input of the RF signal is first divided by 16,
the step size is 125 kHz. A 3.2 MHz crystal can offer a step
size of 100 kHz.
1999 Aug 11
4
Philips Semiconductors
Product specification
2.65 GHz bidirectional I
2
C-bus controlled
synthesizer
Table 1
Write data format; see notes 1 to 13
BYTE
Address
Programmable divider
Charge-pump and test bits
Output ports, control bits
Notes
1. MA1 and MA0: programmable address bits (see Table 3).
2. A: Acknowledge bit.
3. N14 to N0: programmable divider bits.
4. N = N14
×
2
14
+ N13
×
2
13
+ ... + N1
×
2
1
+ N0.
5. CP: charge-pump current. CP = 0: 50
µA;
CP = 1: 220
µA.
6. P7 to P4 = 1: open-collector outputs are active.
7. P7 to P3 and P0 = 0: outputs are in high-impedance state.
8. P3 and P0 = 1: current-limited outputs are active.
9. T1, T0 and OS = 0, 0 and 0: normal operation.
10. T1 = 1: P6 = f
REF
and P7 = f
DIV
.
11. T0 = 1: 3-state charge-pump.
12. OS = 1: Operational amplifier output is switched off (varicap drive disable).
13. X: don’t care.
READ mode: R/W = 1;
see Table 2
Data can be read out of the TSA5055T by setting the R/W
bit to 1. After the slave address has been recognized, the
TSA5055T generates an Acknowledge signal (A) and the
first data byte (status byte) is transferred to the SDA line
(MSB first). Data is valid on the SDA line while the SCL
clock signal is HIGH.
A second data byte can be read out of the TSA5055T if the
processor generates an Acknowledge signal on the SDA
line. End of transmission will occur if the processor does
not send an Acknowledge signal.
MSB
1
0
N7
1
P7
1
N14
N6
CP
P6
0
N13
N5
T1
P5
DATA BYTE
0
N12
N4
T0
P4
0
N11
N3
1
P3
MA1
N10
N2
1
X
MA0
N9
N1
1
X
LSB
0
N8
N0
OS
P0
TSA5055T
COMMAND
A
A
A
A
A
byte 1
byte 2
byte 3
byte 4
byte 5
The TSA5055T will then release the data line to allow the
processor to generate a STOP condition. When ports
P3 to P7 are used as inputs, they must be programmed to
their high-impedance state.
The POR flag (Power-On Reset) is set to 1 at power-on
and when V
CC
goes below 3 V. The flag is reset when an
end of data is detected by the TSA5055T (end of a READ
sequence). Control of the loop is made possible with the
in-lock flag FL, which indicates when the loop is
phase-locked (FL = 1).
1999 Aug 11
5
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