Philips Semiconductors
Product specification
2.7 GHz I
2
C-bus controlled low phase
noise frequency synthesizer
FEATURES
•
Complete 2.7 GHz single chip system
•
Optimized for low phase noise
•
Selectable divide-by-two prescaler
•
Operation up to 2.3 GHz without divide-by-two prescaler
(satellite zero-IF applications) and up to 2.7 GHz with
divide-by-two prescaler
•
Selectable reference divider ratio
•
Selectable crystal or comparison frequency output
•
Four selectable charge pump currents
•
Four selectable I
2
C-bus addresses
•
Standard and fast mode I
2
C-bus
•
I
2
C-bus compatible with 3.3 and 5 V microcontrollers
•
5-level Analog-to-Digital Converter (ADC)
•
Low power consumption
•
Three I/O ports and one output port.
APPLICATIONS
•
Satellite zero-IF and non-zero-IF tuning systems
•
Digital set-top boxes.
GENERAL DESCRIPTION
The TSA5059A is a single chip PLL frequency synthesizer
designed for satellite tuning systems up to 2.7 GHz.
The RF preamplifier drives the 17-bit main divider enabling
a step size equal to the comparison frequency, for an input
frequency up to 2.3 GHz covering the complete satellite
zero-IF frequency range. A fixed divide-by-two additional
prescaler can be inserted between the preamplifier and
the main divider for a frequency between 2.3 and 2.7 GHz.
In this case, the step size is twice the comparison
frequency.
TSA5059A
The comparison frequency is obtained from an on-chip
crystal oscillator that can also be driven from an external
source. Either the crystal frequency or the comparison
frequency can be switched to the XT/COMP output pin to
drive the reference input of another synthesizer or the
clock input of a digital demodulation IC.
Both divided and comparison frequency are compared into
the fast phase detector which drives the charge pump.
The loop amplifier is also on-chip, excepted an external
NPN transistor to drive directly the 33 V tuning voltage.
Control data is entered via the I
2
C-bus; five serial bytes are
required to address the device, select the main divider
ratio, the reference divider ratio, program the four output
ports, set the charge pump current, select the prescaler by
two, select the signal to switch to the XT/COMP output pin
and select a specific test mode. Three of the four output
ports can also be used as input ports and a 5-level ADC is
provided. Digital information concerning the input ports
and the ADC can be read out of the TSA5059A on the SDA
line (one status byte) during a READ operation. A flag is
set when the loop is ‘in-lock’ and is read during a READ
operation, as well as the Power-on reset flag. The device
has four programmable addresses, programmed by
applying a specific voltage at pin AS, enabling the use of
multiple synthesizers in the same system.
ORDERING INFORMATION
TYPE
NUMBER
TSA5059AT
TSA5059ATS
PACKAGE
NAME
SO16
SSOP16
DESCRIPTION
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads; body width 4.4 mm
VERSION
SOT109-1
SOT369-1
2000 Oct 24
2
Philips Semiconductors
Product specification
2.7 GHz I
2
C-bus controlled low phase
noise frequency synthesizer
PINNING
SYMBOL
CP
XTAL
XT/COMP
AS
SDA
SCL
P3
P2
P1
P0
ADC
V
CC
RFA
RFB
GND
DRIVE
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DESCRIPTION
charge pump output
crystal oscillator input
f
xtal
or f
comp
signal output
I
2
C-bus address selection input
I
2
C-bus serial data input/output
I
2
C-bus serial clock input
general purpose output Port 3
general purpose input/output Port 2
general purpose input/output Port 1
general purpose input/output Port 0
analog-to-digital converter input
supply voltage
RF signal input A
RF signal input B
ground supply
external NPN drive output
P3
handbook, halfpage
TSA5059A
CP
XTAL
XT/COMP
AS
SDA
1
2
3
4
16 DRIVE
15 GND
14 RFB
13 RFA
TSA5059A
5
12 VCC
11 ADC
10 P0
9
FCE713
SCL 6
7
P2 8
P1
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The TSA5059A contains all the necessary elements but a
reference source, a loop filter and an external NPN
transistor to control a varicap tuned local oscillator forming
a phase locked loop frequency synthesized source. The IC
is designed in a high speed process with a fast phase
detector to allow a high comparison frequency to reach a
low phase noise level on the oscillator.
The block diagram is shown in Fig.1. The RF signal is
applied at pins RFA and RFB. Thanks to the input
preamplifier a good sensitivity is provided. The output of
the preamplifier is fed to the 17-bit programmable divider
either through a divide-by-two prescaler or directly.
Because of the internal high speed process, the RF divider
is working for a frequency up to 2.3 GHz, without the need
for the divide-by-two prescaler to be used. This prescaler
is needed for frequencies above 2.3 GHz.
The output of the 17-bit programmable divider f
DIV
is fed
into the phase comparator, where it is compared in both
phase and frequency with the comparison frequency f
comp
.
This frequency is derived from the signal present at
pin XTAL, f
xtal
, divided down in the reference divider. It is
possible either to connect a quartz crystal to pin XTAL and
then using the on-chip crystal oscillator, or to feed this pin
with a reference signal from an external source.
The reference divider can have a dividing ratio selected
from 16 different values between 2 and 320 (see Table 8).
2000 Oct 24
5
The output of the phase comparator drives the
charge pump and the loop amplifier section. This amplifier
requires the use of an external NPN transistor. Pin CP is
the output of the charge pump, and pin DRIVE is the pin to
connect the base of the external transistor. This transistor
has its emitter grounded and the collector drives the tuning
voltage to the varicap diode of the Voltage Controlled
Oscillator (VCO). The loop filter has to be connected
between pin CP and the collector of the external NPN
transistor.
In addition, it is possible to drive another PLL synthesizer,
or the clock input of a digital demodulation IC, from
pin XT/COMP. It is possible to select by software either
f
xtal
, the crystal oscillator frequency or f
comp
, the frequency
present after the reference divider at this pin. It is also
possible to switch off this output, in case it is not used.
For test and alignment purposes, it is possible to release
the drive output to be able to apply an external voltage on
it, to select one of the three charge pump test modes, and
to monitor half the f
DIV
at Port P0. See Table 10 for all
possible modes.
Four open-collector output ports are provided on the IC for
general purpose; three of these can also be used as input
ports. A 3-bit ADC is also available.
The TSA5059A is controlled via the two-wire I
2
C-bus.
For programming, there is one 7-bit module address and
bit R/W for selecting READ or WRITE mode.
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