INTEGRATED CIRCUITS
DATA SHEET
TSA5518M
1.3 GHz bidirectional I
2
C-bus
controlled synthesizer
Product specification
File under Integrated Circuits, IC02
1997 Mar 07
Philips Semiconductors
Product specification
1.3 GHz bidirectional I
2
C-bus controlled
synthesizer
FEATURES
•
Complete 1.3 GHz single chip system
•
Low power 5 V, 40 mA
•
I
2
C-bus programming
•
One pin crystal oscillator
•
In-lock flag
•
Varicap drive disable
•
Low radiation
•
Address selection for picture in picture (PIP), DBS tuner,
and so on
•
5-level A/D converter
•
7 bus-controlled ports (4 open-collector outputs and
3 emitter follower outputs), 1 bidirectional port
•
Power-down flag
•
Mixer/oscillator bandswitch output
•
Available in SSOP20 package.
APPLICATIONS
•
TV tuners and front-ends
•
VCR tuners.
QUICK REFERENCE DATA
SYMBOL
V
CC
I
CC
f
i
V
i(rms)
PARAMETER
CONDITIONS
MIN.
4.5
−
80
12
9
40
3.2
−
−
−
−10
−
GENERAL DESCRIPTION
TSA5518M
The device is a single chip PLL frequency synthesizer
designed for TV tuning systems. Control data is entered
via the I
2
C-bus; five serial bytes are required to address
the device, select the oscillator frequency, program the
7 output ports and set the charge-pump current.
The output port P6 is combined with an A/D converter
input. Digital information concerning this port can be read
out of the SDA line (one status byte) during a READ
operation. A flag is set when the loop is ‘in-lock’ and is read
during a READ operation. The device has one fixed
I
2
C-bus address, programmed by applying a specific
voltage on AS input. The phase comparator operates at
7.8125 kHz when a 4 MHz crystal in used. The device
provides a bandswitch output to select the bands of the
mixer/oscillator ICs TDA5330, TDA5630A except
TDA5630/C1 and TDA5730 with the appropriate voltage
level.
TYP.
5
40
−
−
−
−
4
−
−
−
−
−
MAX.
5.5
−
1300
300
300
300
4.48
5
20
10
+80
120
UNIT
V
mA
MHz
mV
mV
mV
MHz
mA
mA
mA
°C
K/W
f
xtal
I
o
T
amb
R
th j-a
supply voltage
supply current
frequency
input voltage level (RMS value) 80 to 150 MHz
150 MHz to 1.0 GHz
1 GHz to 1.3 GHz
crystal oscillator frequency
output current
emitter follower on P4, P5 and P7
open-collector P0, P1 and P2
open-collector P6
operating ambient temperature
thermal resistance from
junction to ambient
ORDERING INFORMATION
TYPE
NUMBER
TSA5518M
PACKAGE
NAME
SSOP20
DESCRIPTION
plastic shrink small outline package; 20 leads; body width 4.4 mm
VERSION
SOT266-1
1997 Mar 07
2
handbook, full pagewidth
1997 Mar 07
fDIV
DIGITAL
PHASE
COMPARATOR
CHARGE
PUMP
1 UD
TO
15-BIT LATCH
DIVIDER RATIO
IN-LOCK
DETECTOR
LOGIC
OP
output
20 PD
15-BIT
PROGRAMABLE
DIVIDER
7.8125 kHz
fref
DIVIDER
N = 512
BLOCK DIAGRAM
Philips Semiconductors
RF1 8
input
RF2 7
PRESCALER
DIVIDE-BY-8
XTAL 19
OSCILLATOR
4 MHz
POWER-DOWN
DETECTOR
1.3 GHz bidirectional I
2
C-bus controlled
synthesizer
SCL 16
OS
LATCH &
CONTROL DATA
8-BIT A/D
CONVERTER
GATE
T1
BAND
SWITCH
5 BS
8-BIT LATCH
PORT INFORMATION
17 VCC
9 GND
3
11 10 14 13
P0 P1 P2 P6 P4 P5 P7
4
3
2
SDA 15
I
2
C-BUS
TRANSCEIVER
ADDRESS
SELECTION
12
AS
MGK115
Product specification
TSA5518M
Fig.1 Block diagram.
Philips Semiconductors
Product specification
1.3 GHz bidirectional I
2
C-bus controlled
synthesizer
PINNING
SYMBOL
UD
P7
P5
P4
BS
n.c
RF2
RF1
GND
P1
P0
AS
P6
P2
SDA
SCL
V
CC
n.c
XTAL
PD
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DESCRIPTION
drive output (UD)
P7 output port
P5 output port
P4 output port
bandswitch output for M/O drive
not connected
UHF/VHF signal input 2
UHF/VHF signal input 1
ground
P1 output port (general purpose)
P0 output port (general purpose)
input for Address Selection
P6 port (output/input for general
purpose ADC)
P2 output port (f
DIV
if the test mode
is active)
I
2
C-bus
serial data input/output
I
2
C-bus serial clock
voltage supply
not connected
crystal oscillator input
charge-pump output (PD)
handbook, halfpage
TSA5518M
UD
1
P7
2
P5
3
P4
4
BS
5
n.c.
6
RF2
7
RF1
8
GND
9
P1
10
MBH947
20
PD
19
XTAL
18
n.c.
17
VCC
16
SCL
TSA5518M
15
SDA
14
P2
13
P6
12
AS
11
P0
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The device is controlled via the two wire I
2
C-bus.
For programming, there is one module address (7 bits)
and the R/W bit for selecting READ or WRITE mode.
Write mode
The write data format is summarized in Table 1. After the
address transmission (first byte), data bytes can be sent to
the device. Four data bytes are needed to fully program
the device. The bus transceiver has an auto increment
facility which permits the programming of the device within
one single transmission (address byte + 4 data bytes).
The device can also be partially programmed on the
condition that the first data byte following the address is
byte 2 or 4. The meaning of the bits in the data bytes is
given in Table 3. The first bit of the first data byte
transmitted indicates whether frequency data (first bit = 0)
or charge pump and port information (first bit = 1) will
follow. Until an I
2
C-bus STOP condition is sent by the
controller, additional data bytes can be entered without the
need to re-address the device. This allows a smooth
frequency sweep for fine tuning or AFC purpose. At
power-on the ports are set to the high-impedance state
(open-collector outputs) or at the HIGH level (emitter
follower outputs). The bandswitch output BS provides a
voltage output suitable for the band selection input of
mixer/oscillator ICs TDA5330, TDA5630A and TDA5730.
It is controlled by B1 and B0 bits or P7, P5 and P4 bits
depending on the BSC bit (see Tables 1 to 4). The
7.8125 kHz reference frequency is obtained by dividing
the output of the 4 MHz crystal oscillator by 512. Because
the input of UHF/VHF signal is first divided-by-8 the step
size is 62.5 kHz. A 3.2 MHz crystal can offer step size of
50 kHz.
1997 Mar 07
4
Philips Semiconductors
Product specification
1.3 GHz bidirectional I
2
C-bus controlled
synthesizer
Table 1
BYTE
1
2
3
4
5
Table 2
address
programmable divider
programmable divider
output ports control bits
Explanation of Table 1
BIT
MA1, MA0
N14, .. , N0
CP
T1, T0, OS
programmable divider bits
N = N14
×
2
14
+ N13
×
2
13
+...+ N1
×
2
1
+ N0
charge pump current
CP = 0 to 50
µA;
CP = 1 to 220
µA
T1 = 0, T0 = 0, OS = 0: normal operation
T1 = 1: P2 = f
DIV
, P6 = f
ref
T0 = 1: 3-state charge pump
OS = 1: operational amplifier output is switched off (varicap drive disable)
BSC
bandswitch control bit
DESCRIPTION
programmable address bits (see Table 7)
Write data format
DESCRIPTION
MS
B
1
0
N7
P7
1
N6
CP
P6
0
N5
T1
P5
0
N4
T0
P4
0
N3
X
N14 N13 N12 N11
N10
N2
P2
N9
N1
B0
P1
TSA5518M
LSB ACKNOWLEDGE
MA1 MA0 0
N8
N0
OS
P0
LOW from device
LOW from device
LOW from device
LOW from device
LOW from device
charge-pump, bandswitch and test bits 1
BSC B1
BSC = 0: bandswitch output is controlled by B1 and B0 bits according to Table 3
BSC = 1: bandswitch output is controlled by P7, P5 and P4 bits according to Table 4
B1, B0
P6, P2, P1 and P0
P4, P5 and P7
X
Table 3
B1
0
0
1
1
bandswitch control bits
P6, P2 .. P0 = 1: open-collector outputs are active
P6, P2 .. P0 = 0: outputs are in high impedance state
P4, P5 and P7 = 1: outputs are at low level
P4, P5 and P7 = 0: emitter follower outputs are active
don’t care
BS output control (BSC = 0)
B0
0
1
0
1
VOLTAGE ON PIN BS
0.25 V
2V
4V
V
CC
Table 4
P7
1
1
0
BS output control (BSC = 1)
P5
1
0
1
P4
0
1
1
VOLTAGE ON PIN BS
0.25 V
2V
4V
1997 Mar 07
5
嵌入式系统
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