UNISONIC TECHNOLOGIES CO., LTD
MJE13007D
NPN BIPOLAR POWER
TRANSISTOR FOR SWITCHING
POWER SUPPLY
APPLICATIONS
DESCRIPTION
The UTC
MJE13007D
is designed for high-voltage,
high-speed power switching inductive circuits where fall time is
critical. It is particularly suited for 115 and 220 V switch mode
applications.
NPN SILICON TRANSISTOR
FEATURES
* V
CEO(SUS)
400V
* 700V Blocking Capability
ORDERING INFORMATION
Ordering Number
Lead Free
MJE13007DL-TA3-T
Halogen Free
MJE13007DG-TA3-T
Package
TO-220
Pin Assignment
1
2
3
B
C
E
Packing
Tube
MJE13007DL-TA3-T
(1)Packing Type
(2)Package Type
(3)Lead Free
(1)T: Tube
(2) TA3: TO-220
(3) G: Halogen Free, L: Lead Free
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Copyright © 2012 Unisonic Technologies Co., Ltd
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MJE13007D
ABSOLUTE MAXIMUM RATING
NPN SILICON TRANSISTOR
PARAMETER
SYMBOL
RATINGS
UNIT
Collector-Emitter Sustaining Voltage
V
CEO
400
V
Collector-Emitter Breakdown Voltage
V
CBO
700
V
Emitter-Base Voltage
V
EBO
9.0
V
8.0
A
Continuous
I
C
Collector Current
Peak (1)
I
CM
16
A
4.0
A
Continuous
I
B
Base Current
Peak (1)
I
BM
8.0
A
12
A
Continuous
I
E
Emitter Current
Peak (1)
I
EM
24
A
Power Dissipation
T
C
= 25°C
P
D
80
W
Junction Temperature
T
J
+150
°C
Storage Temperature
T
STG
-55~+150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
THERMAL DATA
PARAMETER
SYMBOL
RATINGS
UNIT
Junction to Ambient
θ
JA
62.5
°C/W
Junction to Case
θ
JC
1.56
°C/W
Note 1: Pulse Test: Pulse Width = 5.0 ms, Duty Cycle≤10%.
Measurement made with thermocouple contacting the bottom insulated mounting surface of the package
(in a location beneath the die), the device mounted on a heatsink with thermal grease applied at a
mounting torque of 6 to 8•lbs.
ELECTRICAL CHARACTERISTICS
(T
C
=25°C, unless otherwise noted)
PARAMETER
Collector-Emitter Sustaining Voltage
Collector Cutoff Current
Emitter Cutoff Current
DC Current Gain
SYMBOL
V
CEO(SUS)
I
CBO
I
EBO
h
FE1
h
FE2
V
CE(SAT)
TEST CONDITIONS
I
C
=10mA, I
B
=0
V
CES
=700V
V
CES
=700V, T
C
=125°C
V
EB
=9.0V, I
C
=0
I
C
=2.0A, V
CE
=5.0V
I
C
=5.0A, V
CE
=5.0V
I
C
=2.0A, I
B
=0.4A
I
C
=5.0A, I
B
=1.0A
I
C
=8.0A, I
B
=2.0A
I
C
=5.0A, I
B
=1.0A, T
C
=100°C
I
C
=2.0A, I
B
=0.4A
I
C
=5.0A, I
B
=1.0A
I
C
=5.0A, I
B
=1.0A, T
C
=100°C
I
C
=500mA, V
CE
=10V, f=1.0 MHz
V
CB
=10V, I
E
=0, f=0.1MHz
MIN
400
TYP
MAX UNIT
V
0.1
mA
1.0
mA
100
μA
40
30
1.0
V
2.0
V
3.0
V
3.0
V
1.2
V
1.6
V
1.5
V
MHz
pF
0.1
1.5
3.0
0.7
μs
μs
μs
μs
8.0
5.0
Collector-Emitter Saturation Voltage
Base-Emitter Saturation Voltage
V
BE(SAT)
Current-Gain-Bandwidth Product
f
T
Output Capacitance
C
OB
RESISTIVE LOAD (TABLE 1)
Delay Time
t
D
V
CC
=125V, I
C
=5.0A,
Rise Time
t
R
I
B1
=I
B2
=1.0A, t
P
=25μs,
Storage Time
t
S
Duty Cycle≤1.0%
Fall Time
t
F
Note: Pulse Test: Pulse Width≤300μs, Duty Cycle≤2.0%
4.0
14
80
0.025
0.5
1.8
0.23
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TYPICAL THERMAL RESPONSE
NPN SILICON TRANSISTOR
There are two limitations on the power handling ability of a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
-V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate.
The data of Fig. 7 is based on T
C
= 25°C; T
J(PK)
is variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be debated when T
C
≥25°C.
Second breakdown limitations do not
debate the same as thermal limitations. Allowable current at the voltages shown on Fig. 7 may be found at any case
temperature by using the appropriate curve on Fig. 9.
At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
Use of reverse biased safe operating area data (Fig. 8) is discussed in the applications information section.
Transient thermal resistance,
r(t) (NORMALIZED)
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TYPICAL THERMAL RESPONSE(Cont.)
NPN SILICON TRANSISTOR
Table 1. Test Conditions for Dynamic Performance
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING
RESISTIVE
SWITCHING
CIRCUIT VALUES
TEST CIRCUITS
V
CC
=125V
R
C
=25Ω
D1=1N5820 OR EQUIV
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TYPICAL CHARACTERISTICS
1.4
Base-Emitte Saturation Voltage,
V
BE(SAT)
(V)
1.2
1
I
C
=-40°C
0.8
0.6
25°C
100°C
10
5
2
1
0.5
0.2
0.1
0.05
NPN SILICON TRANSISTOR
I
C
/I
B
=5
Collector-Emitte Saturation Voltage,
V
CE(SAT)
(V)
I
C
/I
B
=5
I
C
=-40°C
25°C
0.4
0.01 0.02 0.05 0.1 0.2 0.5 1
2
5 10
100°C
0.02
0.01
0.01 0.02 0.05 0.1 0.2 0.5 1
2
5 10
Collector Current, I
C
(A)
Fig. 2 Base-Emitter Saturation Voltage
Collector Current, I
C
(A)
Fig. 3 Collector-Emitter Saturation Voltage
Collector-Emitter Voltage, V
CE
(V)
10000
Capacitance, C (pF)
C
ib
1000
C
ob
100
T
J
=25°C
Collector Current, I
C
(A)
DC Current Gain, h
FE
100
50
20
10
Extended SOA@1μs,10μs
1μs
10μs
5
T
C
=25°C
2
1ms
DC
1
5ms
0.5
0.2
Bonding wire limit
0.1
Thermal limit
0.05
Second breakdown limit
0.02
0.01
10
curves apply below
rated vceo
10
0.1
1
10
100
1000
20 30 50 70 100 200 300 500 1000
Collector-Emitter Voltage, V
CE
(V)
Fig. 7 Maximum Forward Bias Safe
Operating Area
Reverse Voltage,V
R
(V)
Fig. 6 Capacitance
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