Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> MD80C86/B

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MD80C86/B: 产品描述16-BIT, 5MHz, MICROPROCESSOR, CDIP40, CERDIP-40; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小1MB，共37页; 制造商Rochester Electronics; 官网地址https://www.rocelec.com/

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MD80C86/B概述

16-BIT, 5MHz, MICROPROCESSOR, CDIP40, CERDIP-40

MD80C86/B规格参数

参数名称	属性值
厂商名称	Rochester Electronics
零件包装代码	DIP
包装说明	CERDIP-40
针数	40
Reach Compliance Code	unknown
地址总线宽度	20
位大小	16
边界扫描	NO
最大时钟频率	5 MHz
外部数据总线宽度	16
格式	FIXED POINT
集成缓存	NO
JESD-30 代码	R-GDIP-T40
低功率模式	YES
端子数量	40
最高工作温度	125 °C
最低工作温度	-55 °C
封装主体材料	CERAMIC, GLASS-SEALED
封装代码	DIP
封装形状	RECTANGULAR
封装形式	IN-LINE
认证状态	COMMERCIAL
座面最大高度	5.72 mm
速度	5 MHz
最大供电电压	5.5 V
最小供电电压	4.5 V
标称供电电压	5 V
表面贴装	NO
技术	CMOS
温度等级	MILITARY
端子形式	THROUGH-HOLE
端子节距	2.54 mm
端子位置	DUAL
宽度	15.24 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR

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80C86

Pin Description

The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is

the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).

NUMBER

2-16, 39

SYMBOL

AD15-AD0

TYPE

I/O

DESCRIPTION

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and

data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-

D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory

or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-

dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-

ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”

or “grant sequence”.

ADDRESS/STATUS: During T1, these are the four most significant address lines for memory

operations. During I/O operations these lines are LOW. During memory and I/O operations, sta-

tus information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status

of the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3

are encoded as shown.

This information indicates which segment register is presently being used for data accessing.

These lines are held at high impedance to the last valid logic level during local bus “hold ac-

knowledge” or “grant sequence”.

CHARACTERISTICS

Alternate Data

Stack

Code or None

Data

A19/S6

A18/S5

A17/S4

A16/S3

35-38

BHE/S7

BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to

enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devic-

es tied to the upper half of the bus would normally use BHE to condition chip select functions.

BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be

transferred on the high portion of the bus. The S7 status information is available during T2, T3

and T4. The signal is active LOW, and is held at high impedance to the last valid logic level dur-

ing interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW dur-

ing T1 for the first interrupt acknowledge cycle.

BHE

CHARACTERISTICS

Whole Word

Upper Byte From/to Odd Address

Lower Byte From/to Even address

None

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-

pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on

the 80C86 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-

teed to remain HIGH in T2 until the 80C86 local bus has floated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-

quence”.

READY

READY: is the acknowledgment from the addressed memory or I/O device that will complete the

data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gen-

erator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.

Correct operation is not guaranteed if the Setup and Hold Times are not met.

144

MD80C86/B

MD80C86/B概述

MD80C86/B规格参数

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