UNISONIC TECHNOLOGIES CO., LTD
UR5517
3A DDR BUS TERMINATION
REGULATOR
DESCRIPTION
The
UR5517
is a linear regulator which provides up to 3 Amp
bi-directional sourcing and sinking capability for DDR1/2/3 SDRAM
bus terminator applications. It only requires 20uF of ceramic output
capacitance by a integrated operational amplifier which provides fast
load transient response.
The
UR5517
also includes two control pins, S3 & S5. If S3 were
set in low level, V
TT
will be turned off and left Hi-Z(sleep-state
mode).If setting S5 were set in low level, both V
TT
and V
TTREF
will be
turned off and discharged to ground(soft-off mode).
LINEAR INTEGRATED CIRCUIT
FEATURES
* Input Voltage Range:3~5.5V
* V
LDOIN
Voltage Range:1.2V~3.6V
* DDR1/2/3 Termination Voltage Applications
* Sourcing and Sinking Current up to 3A
* ±20mV Accuracy for V
TT
and V
TTREF
* 10mA Buffered Reference(V
TTREF
)
* Supports High-Z in S3(STR) and Soft-off in S5(Shutdown)
* Integrated Divider Tracks 1/2 V
DDQSNS
for Both V
TT
&V
TTREF
* Built-In Soft-Start
* Current Limiting Protection
* Thermal Shutdown Protection
ORDERING INFORMATION
Ordering Number
Lead Free
Halogen Free
UR5517L-SM2-R
UR5517G-SM2-R
UR5517L-SM2-T
UR5517G-SM2-T
UR5517L-SM2 -R
(1)Packing Type
(2)Package Type
(3)Lead Free
Package
MSOP-10
MSOP-10
Packing
Tape Reel
Tube
(1) R: Tape Reel, T: Tube
(2) SM2: MSOP-10
(3) G: Halogen Free, L: Lead Free
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QW-R102-041.B
UR5517
PIN CONFIGURATIONS
LINEAR INTEGRATED CIRCUIT
PIN DESCRIPTION
(Note)
PIN NAME
PIN TYPE
PIN DESCRIPTION
V
DDQSNS
I
V
DDQ
sense input
V
LDOIN
I
Power supply for the V
TT
& V
TTREF
output stage
V
TT
O
Output voltage for connection to termination resistors, equal to V
DDQSNS
/2
PGND
O
Power ground output for the V
TT
output
V
TTSNS
I
Voltage sense input for the V
TT
. Connect to plus terminal of the output capacitor
V
TTREF
O
Buffered output that is a reference output, equal to V
DDQSNS
/2
S3
I
Active low suspend to RAM mode control pin, V
TT
is turned off and left Hi-Z
GND
I
Ground
S5
I
Active low shutdown control pin, both V
TT
&V
TTREF
are turned off and discharged to ground
V
IN
I
Analog input pin
Note:Recommend connecting the Thermal Pad to the GND for the excellent power dissipation.
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QW-R102-041.B
UR5517
BLOCK DIAGRAM
LINEAR INTEGRATED CIRCUIT
V
DDQSNS
OTP
V
IN
V
LDOIN
S3
S5
STB
SD
V
DDQSNS
/
2 *1.05
V
TTSNS
+
V
TT
V
TTREF
+
V
DDQSNS
/2
V
DDQSNS
/
2 *0.95
PGOOD
Current
Limit
GND
PGND
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UR5517
LINEAR INTEGRATED CIRCUIT
ABSOLUTE MAXIMUM RATING
(unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage(V
IN
,V
LDOIN
,V
DDQSNS
,S3,S5)
-0.3~6
V
Power Ground Output for the V
TT
Output
P
GND
-0.3~0.3
V
Output Voltage(V
TT
,V
TTREF
)
V
TT
,V
TTREF
-0.3~V
LDOIN
+0.3
V
Junction Temperature
T
J
160
℃
Storage Temperature
T
STG
-55 ~ +160
℃
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING CONDITIONS
(Note1, 2)
SYMBOL
MIN
TYP
MAX
Input Voltage
V
IN
3
5.5
STR and Shutdown Voltage
S3,S5
-0.1
5.5
V
DDQ
Sense Input
V
DDQSNS
1.3
3.6
Power Supply for the V
TT
and V
TTREF
Output Stage
V
LDOIN
1.2
3.6
Power Ground Output for the V
TT
Output
P
GND
-0.1
0.1
Operating Temperature
T
A
-40
85
Note: 1. All voltage values are with respect to the network ground terminal unless otherwise noted.
2. Please always keep V
LDOIN
,V
TTSNS
,V
DDQSNS
,S3,S5 lower than V
IN
on operation.
PARAMETER
UNIT
V
V
V
V
V
℃
ELECTRICAL CHARACTERISTICS
(V
IN
=5V,V
LDOIN
=V
DDQSNS
=2.5V,
T
A
=25℃.Unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDITIONS
S5=Hi,S3=Hi, no load(Normal)
I
VIN
Current of V
IN
I
VINSTB
S5=Hi,S3=Lo, no load(Standby)
I
VINSDN
S5=Lo,S3=Lo, no load(Shutdown)
S5=Hi,S3=Hi, no load(Normal)
I
VLDOIN
Current of V
LDOIN
I
VLDOINSTB
S5=Hi,S3=Lo, no load(Standby)
I
VLDOINSDN
S5=Lo,S3=Lo, no load(Shutdown)
Input Impedance of V
DDQSNS
Z
VDDQSNS
S5=Hi,S3=Hi
Input Current of V
TTSNS
I
VTTSNS
S5=Hi,S3=Hi
DDR1(V
LDOIN
=V
DDQSNS
=2.5V)
Output Voltage of V
TT
V
TT
DDR2(V
LDOIN
=V
DDQSNS
=1.8V)
DDR3(V
LDOIN
=V
DDQSNS
=1.5V)
I
VTT
=0
Load Regulation of V
TT
VosV
TT
∣
I
VTT
∣
<1.5A
(V
TTREF
-V
TT
)
∣
I
VTT
∣
<3A
V
TT
=V
DDQSNS
/2*0.95,PGOOD=HI
Source Current Limit of V
TT
I
VTTOCLSRC
V
TT
=0
V
TT
=V
DDQSNS
/2*1.05,PGOOD=HI
Sink Current Limit of V
TT
I
VTTOCLSNK
V
TT
=V
DDQSNS
Leakage Current of V
TT
I
VTTLK
S5=Hi,S3=Lo
Discharge Current of V
TT
I
VTTDIS
S5=Lo, V
DDQSNS
=0V,V
TT
=0.5V
DDR1(V
LDOIN
=V
DDQSNS
=2.5V)
Output Voltage of V
TTREF
V
TTREF
DDR2(V
LDOIN
=V
DDQSNS
=1.8V)
DDR3(V
LDOIN
=V
DDQSNS
=1.5V)
Load Regulation of V
TTREF
ΔV
TTREF
∣
I
VTTREF
∣
<10mA
High Level Input Voltage
V
IH
S3 & S5 pin
Low Level Input Voltage
V
IL
S3 & S5 pin
Logic Input Leakage Current
I
ILEAK
S3 & S5 pin
Thermal Shutdown Temperature
T
SD
V
IN
=3V~5.5V
Thermal Shutdown Hysteresis
ΔT
SD
V
IN
=3V~5.5V
MIN
0.5
TYP
0.8
110
0.03
0.1
0.1
200
0.3
1.25
0.9
0.75
-20
-30
-40
3
1.5
3
1.5
10
MAX
2
200
1
2
10
1
1
UNIT
mA
uA
uA
mA
uA
uA
kΩ
uA
V
20
30
40
4
2
4
2
0.01
20
1.25
0.9
0.75
20
1
1
160
20
mV
A
A
uA
mA
V
mV
V
uA
℃
-20
1.6
-1
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QW-R102-041.B
UR5517
TYPICAL APPLICATIONS CIRCUIT
LINEAR INTEGRATED CIRCUIT
DDR2
1.8V
V
DDQSNS
V
LDOIN
Vo1
V
TT
PGND
Io1
RL1
2*10uF
V
IN
S5
GND
S3
V
TTREF
0.1uF
5V
RS5
10K
V5
RS3
10K
V3
V
TTSNS
C1
RL2
Io2
C2
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QW-R102-041.B