F81485
F81485
5V Low Power RS-485 Interface Transceiver
Release Date: Jan, 2012
Version: V0.11P
Jan, 2012
V0.11P
F81485
F81485 Datasheet Revision History
Version
V0.10P
V0.12P
Date
2011/12
2012/01
Page
-
-
Revision History
Preliminary
Made Clarification and Correction
Update Top Marking Specification
Update Differential Input Threshold Spec.
Please note that all data and specifications are subject to change without notice. All the trade marks of products
and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of
these products can reasonably be expected to result in personal injury. Customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting
from such improper use or sales.
Jan, 2012
V0.11P
F81485
Table of Content
1
2
3
4
5
6
7
8
9
General Description ................................................................................................................................................. 4
Feature List.............................................................................................................................................................. 4
Pin Configuration ..................................................................................................................................................... 5
Pin Description ........................................................................................................................................................ 5
Electrical Characteristics Request .......................................................................................................................... 7
Ordering Information ............................................................................................................................................. 10
Top Marking Specification ..................................................................................................................................... 10
Package Spec. ...................................................................................................................................................... 11
Application Circuit .................................................................................................................................................. 12
Jan, 2012
V0.11P
F81485
1
General Description
The F81485 is a CMOS design, features with single 5 V power supply, and low power differential
bus/line transceiver suitable for the multipoint data transmission EIA standard RS485 and RS422
applications. The extended common-mode range is
−7
V to +12 V. Both the driver and the receiver
can be enabled independently. The driver and receiver feature three-state outputs, with the driver
outputs maintaining high impedance over the entire common-mode range. Excessive power
dissipation caused by the bus contention or faults is prevented by a thermal shutdown circuit which
forces the driver outputs into a high impedance state. The receiver contains a fail-safe feature that
results in a logic high output state if the inputs are unconnected (floating). Up to 32 transceivers can
be connected simultaneously on a bus, but only one driver should be enabled at any time. The
F81485 features extremely fast switching speeds. Minimal driver propagation delays permit
transmission at data rates up to 5 Mbps while low skew minimizes EMI interference. All inputs and
outputs contain protection against ESD; all driver outputs feature high source and sink current
capability. An epitaxial layer is used to guard against latch-up.
2
Feature List
Single 5V Supply
Meets EIA RS-485 standard
High speed, low power BiCMOS
-7V to 12V Bus Common-Mode Range Permits
±7V
Ground Difference Between Devices on the Bus
ESD
±8KV
Contact
Thermal Shutdown Protection
Driver Maintains High Impedance in Three-State or with the Power Off
70mV Typical Input Hysteresis
Driver propagation delay: 10 ns typical
Receiver propagation delay: 15 ns typical
High-Z outputs with power off
Pin Compatible with the ADM485, SP485
8 Pin SOP Packaging
4
Jan, 2012
V0.11P
F81485
3
Pin Configuration
F81485
RO
RE
DE
DI
1
2
3
4
D
R
8
7
6
5
Vcc
B
A
GND
4
IN
t
O
4
P
Pin Description
- TTL level input pin.
- Output pin with 4mA driver.
- Power.
4.1. Power Pin
Pin
5
8
Pin Name
GND
VCC
Type
P
P
Description
GND.
4.75V< VCC < 5.25V power supply voltage input.
4.2. Transceiver
Pin
1
2
Pin Name
RO
RE#
Type
O
4
IN
t
Description
Receiver Output. When enabled (RE# is low), then if
A > B by 200 mV, RO is high.
A < B by 200 mV, RO is low.
Active Low Receiver Output Enable pin.
A low level enables the receiver output, RO.
A high level places it in a high impedance state.
Active High Driver Output Enable.
A high level enables the driver differential outputs, A and
B. The chip will function as a line driver.
A low level places it in a high impedance state.
The chip
will function as a line receiver.
3
DE
IN
t
5
Jan, 2012
V0.11P
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