HD49815TF
Digital Camera Signal Processor
ADE-207-316 (Z)
1st Edition
Sep. 1999
Description
The HD49815TF is a CMOS IC that has been developed as a digital signal-processing IC for CCD-camera
digital-signal-processing systems.
Functions
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CCD-sensor drive-pulse generation (TG)
Digital AGC (automatic gain control)
Color signal separation circuit
RGB matrix
RGB gain
RGB and Y gamma
Color-difference matrix
Enhancer
RGB and Y setup
Digital I/F (4:2:2)
Zoom control
Mirror reversal
Synchronization signal generator for encoding (SSG)
AWB, AE, and AF detection
Two-channel 8-bit D/A converter
Features
•
The HD49815TF provides camera-signal processing, TG, SSG, zoom, and D/A functions and other
functions in a single chip and supports high system-integration level.
•
In conjunction with the HD49323AF-01 (CDS/AGC + 10-bit ADC) and the control microcomputer, the
HD49815TF forms a three-chip kit that can implement an optimal CCD-camera digital-signal-
processing system.
•
The HD49815TF provides the zoom function and controls the 1- to 256- times linear zoom. It also
provides the half-mirror function.
HD49815TF
Features
(cont)
•
Since the HD49815TF can be made compatible with the former product, HD49811TFA, through
software, a shorter development term is enabled.
•
Since software controls AWB, AE, and AF, any protocol can be prepared according to the camera
shooting conditions.
•
Programmable TG enables use of any CCD device.
System Block Diagram
HD49815TF
Lens
CCD HD49323AF-01
CDS/AGC+
10-bit ADC
Input
line
memory
Color
processing
Luminance
processing
Micro-
processor
I/F
Zoom
processing
C-signal output
Y-signal output
R-Y/B-Y
digital output
Y-signal
digital output
TG
SSG
V.Driver
Encode
DAC
System
control
AE
(iris)
control
AWB
(white
balance)
control
8-bit single-chip microcomputer (H8 series)
2
HD49815TF
Pin Arrangement
DSP_MCK
CPREF
XSG2
XSG1
XV4
XV3
XV2
XV1
V
DD
XSUB
DKF_LD
T_CP(TEST)
TY_K
SDI
SDCK
SLD
SDO
EP(1)
EP(2)
BF
HD_IN
M_CK
V
DD
V
SS
FV
HD
CBLK
CSYNC
SCBLK
HSYNC
ID
IDP
V
DD
V
SS
X1I
X1O
IDS
MCK_S
RESET
1
2
3
4
5
6
7
8
9
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
AD(10)
ADCK
AD(1)
AD(2)
AD(3)
AD(4)
AD(5)
AD(6)
AD(7)
AD(8)
AD(9)
OBP
SP2
SP1
V
DD
V
DD
V
DD
V
SS
RG
H2
H1
ZOOM_HD
FP
NME
CPI(1)
CPI(2)
CPI(3)
CPI(4)
CPI(5)
CPI(6)
CPI(7)
CPI(8)
CPO(1)
CPO(2)
CPO(3)
CPO(4)
V
SS
V
DD
CPO(5)
CPO(6)
CPO(7)
CPO(8)
YPI(1)
YPI(2)
YPI(3)
YPI(4)
YPI(5)
YPI(6)
YPI(7)
YPI(8)
YPO(1)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
TFP-120
30
61
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
X2I
X2O
V
SS
V
SS
V
SS
V
SS
V
SS
REXT
Y_OUT
V
SS
VR
YPO(8)
YPO(7)
YPO(6)
YPO(5)
YPO(4)
YPO(3)
C_OUT
NRYBY
YPO(2)
PLL_P
PLL_N
DICK
AV
DD
AV
DD
AV
DD
CBU
FSC
CBL
V
DD
(Top view)
3
HD49815TF
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Symbol
XSUB
DKF_LD
T_CP
TY_K
SDI
SDCK
SLD
SDO
EP (1)
EP (2)
BF
HD_IN
M_CK
V
DD
V
SS
FV
HD
CBLK
CSYNC
SCBLK
HSYNC
ID
IDP
V
DD
V
SS
X1I
X1O
IDS
MCK_S
RESET
Pin Name
CCD shutter pulse
Line input LD
Test
Title SW
State data input
State data clock
State data load pulse
AWB, AE, data output
AE window pulse 1
AE window pulse 2
Burst flag
External CSYNC input
Microprocessor clock
V
CC
2
GND
Field vertical output
HD output
Blanking pulse
SYNC output
SC blanking pulse
Horizontal SYNC
Identity
Identity pulse
V
CC
2
GND
X’tal 1 input
X’tal 1 output
Line ID reset input
MCK output SW
Reset
I/O
O
I
I
I
I
I
I
O
O
O
O
I
O
—
—
O
O
O
O
O
O
O
O
—
—
I
O
I
I
I
Description
CCD control pulse
Line input dedicated load
Test pin (GND input)
Title-killer SW (1 = On, 0 = Off)
State data-setting data input
State data-setting clock
State data-latch pulse
AWB, AE, and AF detection-data output
Iris detection-area-setting pulse:
SP-A7 [8] output changeover
Iris detection-area-setting pulse:
SP-A7 [8] output changeover
Burst flag output
External CSYNC input
Microprocessor clock output
(1/2 or 1/4 dividing of X’tal 1)
3.3 V power supply
GND
Vertical synchronization pulse
Horizontal synchronization pulse
Blanking pulse
SYNC pulse
Subcarrier blanking pulse (SECAM)
Horizontal SYNC pulse (SECAM)
SECAM determination pulse
SECAM determination pulse
3.3 V power supply
GND
2fsc oscillator input
2fsc oscillator output
Line-determination-signal input
Pin 13 MCK dividing setting SW
(1 = 1/2, 0 = 1/4)
Reset: to restore the initial data settings
I/O
Format
ZC2R
ICS
IC
ICD
IC
ICS
ICS
ZC2R
ICZC2R
ICZC2R
ICZC2R
ICSD
OC2R
VCCI
GNDI
ICZC2R
ICZC2R
ICZC2R
ICZC2R
ICZC2R
OC2R
OC2R
ICZC2R
VCCC
GNDC
IQ3
OQ3
ICD
IC
ICS
4
HD49815TF
Pin Description
(cont)
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
PLL_N
PLL_P
VR
X2I
X2O
FSC
V
SS
AV
DD
V
SS
AV
DD
V
SS
C_OUT
CBU
CBL
REXT
Y_OUT
V
SS
AV
DD
V
SS
V
DD
V
SS
DICK
NRYBY
YPO (8)
YPO (7)
YPO (6)
YPO (5)
YPO (4)
YPO (3)
YPO (2)
YPO (1)
YPI (8)
YPI (7)
YPI (6)
Pin Name
PLL negative
PLL positive
Vertical reset
X’tal 2 input
X’tal 2 output
Sub carrier frequency
GND
Analog V
CC
2
GND
Analog V
CC
2
GND
C analog signal output
Current buffer upper
Current buffer lower
Reference resister EXT
Y analog signal output
GND
Analog V
CC
2
GND
V
CC
2
GND
Digital interface clock
R-Y, B-Y phase output
Y parallel output (8); MSB
Y parallel output (7)
Y parallel output (6)
Y parallel output (5)
Y parallel output (4)
Y parallel output (3)
Y parallel output (2)
Y parallel output (1) ; LSB
Y parallel input (8); MSB
Y parallel input (7)
Y parallel input (6)
I/O
O
O
I
I
O
O
—
—
—
—
—
O
I
I
I
O
—
—
—
—
—
O
O
O
O
O
O
O
O
O
O
I
I
I
Description
PLL signal output
PLL signal output
Vertical synchronization signal input
4fsc oscillator input
4fsc oscillator output
fsc output
GND
Analog system power supply: 3.3 V
GND
Analog system power supply: 3.3 V
GND
Chrominance-signal analog output
D/A upper current source
D/A lower current source
Reference voltage input
Luminance-signal analog output
GND
Analog system power supply: 3.3 V
GND
Digital system power supply: 3.3 V
GND
Digital interface clock output
Color-difference signal phase clock
Luminance-signal digital output MSB
Luminance-signal digital output
Luminance-signal digital output
Luminance-signal digital output
Luminance-signal digital output
Luminance-signal digital output
Luminance-signal digital output
Luminance-signal digital output LSB
Luminance-signal digital input MSB
Luminance-signal digital input
Luminance-signal digital input
I/O
Format
ZC2
ZC2
ICSD
IQ2
OQ2
ICZC2R
GNDA
VCCA
GNDA
VCCA
GNDA
OA
IA
IA
IA
OA
GNDA
VCCA
GNDA
VCCI
GNDI
ICZC2R
ICZC2R
OC2R
OC2R
OC2R
OC2R
OC2R
OC2R
OC2R
OC2R
ICD
ICD
ICD
5
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