Physical Layer Transceiver is designed to maximize the speed of
SpaceWire links implemented in Field Programmable Gate
Arrays. The UT200SpWPHY01 is designed to handle the critical
timing issues associated with the SpaceWire data/strobe encoding
scheme.
Receiver Fail-Safe
The UT200SpWPHY01 SpaceWire Physical Layer Transceiver is
a high gain, high speed device that amplifies a small differential
signal (20mV) to TTL logic levels. Due to the high gain and tight
threshold of the receiver, care should be taken to prevent noise
from appearing as a valid signal.
The receiver’s internal fail-safe circuitry is designed to source/
sink a small amount of current, providing fail-safe protection (a
stable known state of HIGH output voltage) for floating,
terminated or shorted receiver inputs.
1.
Open Input Pins.
If an application requires an unused
channel, the inputs should be left OPEN. Do not tie unused
receiver inputs to ground or any other voltages. The input
is biased by internal high value pull up and pull down
resistors to set the output to a HIGH state. This internal
circuitry will guarantee a HIGH, stable output state for
open inputs.
2.
Terminated Input.
If the driver is disconnected (cable
unplugged), or if the driver is in a three-state or power-off
condition, the receiver output will again be in a HIGH state,
even with the end of cable 100Ω termination resistor across
the input pins. The unplugged cable can become a floating
antenna which can pick up noise. If the cable picks up more
than 10mV of differential noise, the receiver may see the
noise as a valid signal and switch. To insure that any noise
is seen as common-mode and not differential, a balanced
interconnect should be used. Twisted pair cable offers
better balance than flat ribbon cable.
Shorted Inputs.
If a fault condition occurs that shorts the receiver
inputs together, thus resulting in a 0V differential input voltage,
the receiver output remains in a HIGH state. Shorted input fail-
safe is not supported across the common-mode range of the device
(V
SS
to 2.4V). It is only supported with inputs shorted and no
external common-mode voltage applied.
2
Table 1
:
SpaceWire Physical Layer Transceiver Device Op-
eration Truth Table
TxOE
0
1
0
0
1
1
1
1
1
RST
0
1
1
1
0
0
1
1
1
LclLBE
X
0
0
1
X
X
0
1
1
RmtLBE
X
0
X
X
0
1
1
0
1
Tx
Outputs
Hi-Z
CMOS
Tx Inputs
Hi-Z
Hi-Z
0
LVDS
Rx Inputs
LVDS
Rx Inputs
CMOS
Tx Inputs
LVDS
Rx Inputs
Rx
Outputs
Hi-Z
LVDS
Rx Inputs
LVDS
Rx Inputs
CMOS
Tx Inputs
Hi-Z
Hi-Z
LVDS
Rx Inputs
CMOS
Tx Inputs
CMOS
Tx Inputs
RADIATION
Parameter
Total Ionizing Dose (TID)
Single Event Latchup (SEL)
1, 2
SEU Saturated Cross-Section (σ
sat
)
Onset Single Event Upset (SEU) LET
Threshold
3
Neutron Fluence
Dose Rate Upset
Dose Rate Survivability
Limit
>3E5
and
1E6
>109
1.0E-8
109
1.0E14
TBD
TBD
Units
rads(Si)
MeV-cm
2
/mg
cm
2
/device
MeV-cm
2
/mg
n/cm
2
rads(Si)/sec
rads(Si)/sec
Notes:
1. The UT200SpW02 are latchup immune to particle LETs >109 MeV-cm
2
/mg.
2. Worst case temperature and voltage of T
C
= +125
o
C, V
DD
= 3.6V,
V
DD
Q1/Q3/Q4 = 3.6V for SEL.
3. Worst case temperature and voltage of T
C
= +25
o
C, V
DD
= 3.0V,
V
DD
Q1/Q3/Q4 = 3.0V for SEU.
4.Adams 90% worst case particle environment, Geosynchronous orbit, 100mils
of Aluminum shielding.
3
28-pin Flatpack Pin Description
Pin Name
LclLBE
Pin
Number
1
Pin Type
LVCMOS Input
1
Description
Local Loopback Enable
0: No loopback, received data comes from LVDS Rx
inputs (RxD+, ...)
1: Local loopback, received data comes from LVCMOS
Tx inputs (TxD0, ...)
Remote Loopback Enable
0: No loopback, Transmit LVDS data comes from the
LVCMOS Tx inputs (TxD0, ...)
1. Remote Loopback, Transmit LVDS data comes from
LVDS Rx inputs.
LVDS Rx differential positive Data input
LVDS Rx differential negative Data input
LVDS Rx differential positive Strobe input
LVDS Rx differential negative Strobe input
VDD 3.3V power supply
Vss 0V
LVDS Output
LVDS Output
LVDS Output
LVDS Output
LVCMOS Input
1
LVDS Tx differential positive Strobe output
LVDS Tx differential negative Strobe output
LVDS Tx differential positive Data output
LVDS Tx differential negative Data output
TxOE=High: Enables LVDS transmit
TxOE=Low: Tri-states LVDS transmit
RmtLBE
2
LVCMOS Input
1
RxD+
RxD-
RxS+
RxS-
V
DD
GND
TxS+
TxS-
TxD+
TxD-
TxOE
RxDR
RxDF
RxClk
RST
TxClk
3
4
5
6
7, 22, 28
8,14,21,27
9
10
11
12
13
26
25
24
23
20
LVDS Input
LVDS Input
LVDS Input
LVDS Input
LVCMOS Output Receiver rising edge (even) bit output (See Figure 7)
LVCMOS Output Receiver falling edge (odd) bit output (See Figure 7)
LVCMOS Output Receiver clock output
LVCMOS Input
1
RST must remain low for 3 clock cycles before
transitioning high, and must transition high 3 clock
cycles before valid data.
Clock input to transmitter used to clock LVDS output.
Any phase relationship is allowed between TxClk &
WrClk but both must come from the same clock source
and TxClk must be twice the frequency of the WrClk.
Transmitter input data Clock used to clock CMOS input
to transmitter. Any phase relationship is allowed between
TxClk & WrClk but both must come from the same clock
source and WrClk must 1/2 of TxClk.
First (even) bit of 2bit parallel strobe input to transmitter
Second (odd) bit of 2bit parallel strobe input to
transmitter
First, even bit of 2bit parallel data input to transmitter
Second, odd bit of 2bit parallel data input to transmitter
4
LVCMOS Input
1
WrClk
19
LVCMOS Input
1
TxS0
TxS1
TxD0
TxD1
18
17
16
15
LVCMOS Input
LVCMOS Input
LVCMOS Input
LVCMOS Input
Note 1. LVTTL compatible
PIN CONFIGURATION
LclLBE
RmtLBE
RxD+
RxD-
RxS+
RxS-
V
DD
GND
TxS+
TxS-
TxD+
TxD-
TxOE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
GND
RxDR
RxDF
RxClk
RST
V
DD
GND
TxClk
WrClk
TxS0
TxS1
TxD0
TxD1
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
PARAMETER
DC supply voltage
Voltage on any pin during operation
Voltage on any LVDS pin during cold
spare
2
T
STG
P
D
Θ
JC
I
I
Storage temperature
Maximum power dissipation
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 4.0V
-0.3 to (V
DD
+ 0.3V)
-.3 to 4.0V
-65 to +150°C
432 mW
10°C/W
±
10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
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卡巴斯基的安全研究人员称其发现了如何攻击Intel微处理器的远程攻击代码，据传，这一代码可以通过TCP/IP包和JavaScript代码到达用户系统。 目前受影响的系统包括Windows XP，Vista，Windows Server 2003，Windows Server 2008，Linux甚至是BSD和Mac。但所幸大多数错误可以由Intel和BIOS厂商联合进行修复。 卡...[详细]
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