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5962F9863401VCC: 产品描述AC SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16; 产品类别逻辑逻辑; 文件大小38KB，共2页; 制造商Renesas(瑞萨电子); 官网地址https://www.renesas.com/

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5962F9863401VCC概述

AC SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16

5962F9863401VCC规格参数

参数名称	属性值
厂商名称	Renesas(瑞萨电子)
零件包装代码	DIP
包装说明	DIP,
针数	16
Reach Compliance Code	unknown
系列	AC
JESD-30 代码	R-CDIP-T16
JESD-609代码	e4
逻辑集成电路类型	D FLIP-FLOP
位数	1
功能数量	6
端子数量	16
最高工作温度	125 °C
最低工作温度	-55 °C
输出极性	TRUE
封装主体材料	CERAMIC, METAL-SEALED COFIRED
封装代码	DIP
封装形状	RECTANGULAR
封装形式	IN-LINE
传播延迟（tpd）	23 ns
认证状态	Not Qualified
筛选级别	MIL-PRF-38535 Class V
座面最大高度	5.08 mm
表面贴装	NO
技术	CMOS
温度等级	MILITARY
端子面层	GOLD
端子形式	THROUGH-HOLE
端子节距	2.54 mm
端子位置	DUAL
总剂量	300k Rad(Si) V
触发器类型	POSITIVE EDGE
宽度	7.62 mm

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ACS174MS

Data Sheet

July 1999

File Number

4762

Radiation Hardened Hex D-Type Flip-Flop

with Reset

The Radiation Hardened ACS174MS is a Hex D-Type Flip-

Flop with Reset. Information at the D input is transferred to

the Q output on the positive-going transition of the clock. All

six flip-flops are controlled by a common clock (CP) and a

common reset (MR). Resetting is accomplished by a LOW

level independent of the clock. All inputs are buffered and

the outputs are designed for balanced propagation delay

and transition times.

The ACS174MS is fabricated on a CMOS Silicon on

Sapphire (SOS) process, which provides an immunity to

Single Event Latch-up and the capability of highly reliable

performance in any radiation environment. These devices

offer significant power reduction and faster performance

when compared to ALSTTL types.

Speciﬁcations for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed below must be used when ordering.

Detailed Electrical Speciﬁcations for the ACS174MS are

contained in SMD 5962-98634. A “hot-link” is provided

on our homepage for downloading.

http://www.intersil.com/spacedefense/spaceselect.htm

Features

• QML Qualiﬁed Per MIL-PRF-38535 Requirements

• 1.25 Micron Radiation Hardened SOS CMOS

• Radiation Environment

- Latch-Up Free Under Any Conditions

- Total Dose (Max.) . . . . . . . . . . . . . . . . . 3 x 10

RAD(Si)

- SEU Immunity . . . . . . . . . . . . . <1 x 10

-10

Errors/Bit/Day

- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm

)

• Input Logic Levels. . . . V

= (0.3)(V

), V

= (0.7)(V

)

• Output Current

. . . . . . . . . . . . . . . . . . . . . . . . . . ±12mA

(Min)

• Quiescent Supply Current . . . . . . . . . . . . . . . 10µA (Max)

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 23ns (Max)

Applications

• High Speed Control Circuits

• Sensor Monitoring

• Low Power Designs

Ordering Information

ORDERING NUMBER

5962F9863401VCC

ACS174D/SAMPLE-03

5962F9863401VXC

ACS174K/SAMPLE-03

5962F9863401V9A

INTERNAL MARKETING

NUMBER

ACS174DMSR-03

ACS174D/SAMPLE-03

ACS174KMSR-03

ACS174K/SAMPLE-03

ACS174HMSR-03

TEMP. RANGE (

-55 to 125

PACKAGE

16 Ld SBDIP

16 Ld Flatpack

Die

DESIGNATOR

CDIP2-T16

CDFP4-F16

Pinouts

ACS174MS

(SBDIP)

TOP VIEW

MR 1

Q0 2

D0 3

D1 4

Q1 5

D2 6

Q2 7

GND 8

16 V

15 Q5

14 D5

13 D4

12 Q4

11 D3

10 Q3

9 CP

GND

ACS174MS

(FLATPACK)

TOP VIEW

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

5962F9863401VCC相似产品对比

	5962F9863401VCC	5962F9863401VXC	5962F9863401V9A	ACS174DMSR-03	ACS174KMSR-03	ACS174HMSR-03
描述	AC SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16	AC SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, DFP-16	AC SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, UUC16, DIE-16	AC SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16	AC SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP16, CERAMIC, DFP-16	AC SERIES, HEX POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, UUC16, DIE-16
零件包装代码	DIP	DFP	DIE	DIP	DFP	DIE
包装说明	DIP,	DFP, FL16,.3	DIE,	DIP,	DFP,	DIE,
针数	16	16	16	16	16	16
Reach Compliance Code	unknown	not_compliant	unknown	unknown	unknown	unknown
系列	AC	AC	AC	AC	AC	AC
JESD-30 代码	R-CDIP-T16	R-CDFP-F16	S-XUUC-N16	R-CDIP-T16	R-CDFP-F16	X-XUUC-N16
逻辑集成电路类型	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
位数	1	1	1	1	1	1
功能数量	6	6	6	6	6	6
端子数量	16	16	16	16	16	16
输出极性	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
封装主体材料	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	UNSPECIFIED
封装代码	DIP	DFP	DIE	DIP	DFP	DIE
封装形状	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR	UNSPECIFIED
封装形式	IN-LINE	FLATPACK	UNCASED CHIP	IN-LINE	FLATPACK	UNCASED CHIP
传播延迟（tpd）	23 ns	23 ns	23 ns	23 ns	23 ns	23 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
筛选级别	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
表面贴装	NO	YES	YES	NO	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子形式	THROUGH-HOLE	FLAT	NO LEAD	THROUGH-HOLE	FLAT	NO LEAD
端子位置	DUAL	DUAL	UPPER	DUAL	DUAL	UPPER
总剂量	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V	300k Rad(Si) V
触发器类型	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	-
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-
座面最大高度	5.08 mm	2.92 mm	-	5.08 mm	2.92 mm	-
温度等级	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	-
端子节距	2.54 mm	1.27 mm	-	2.54 mm	1.27 mm	-
宽度	7.62 mm	6.73 mm	-	7.62 mm	6.73 mm	-
Base Number Matches	-	1	1	1	1	-

5962F9863401VCC

5962F9863401VCC概述

5962F9863401VCC规格参数

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