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CY62177DV30_12

产品描述32-Mbit (2 M × 16) Static RAM
文件大小264KB,共13页
制造商Cypress(赛普拉斯)
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CY62177DV30_12概述

32-Mbit (2 M × 16) Static RAM

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CY62177DV30 MoBL
®
32-Mbit (2 M × 16) Static RAM
Features
Very high speed: 55 ns
Wide voltage range: 2.20 V–3.60 V
Ultra-low active power
Typical active current: 2 mA at f = 1 MHz
Typical active current: 15 mA at f = f
max
Ultra low standby power
Easy memory expansion with CE
1
, CE
2
and OE features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
Packages offered in a 48-ball fine ball grid array (FBGA)
applications such as cellular telephones.The device also has an
automatic power-down feature that significantly reduces power
consumption. The device can also be put into standby mode
when deselected (CE
1
HIGH or CE
2
LOW or both BHE and BLE
are HIGH). The input/output pins (I/O
0
through I/O
15
) are placed
in a high-impedance state when: deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE HIGH), both Byte High Enable
and Byte Low Enable are disabled (BHE, BLE HIGH), or during
a write operation (CE
1
LOW, CE
2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If
Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is written into the location specified on the address
pins (A
0
through A
20
). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
20
).
Reading from the device is accomplished by taking Chip Enables
(CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins will appear on I/O
0
to I/O
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O
8
to
I/O
15
. See the truth table for a complete description of read and
write modes.
Functional Description
The CY62177DV30 is a high-performance CMOS static RAM
organized as 2M words by 16 bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL
®
) in portable
Logic Block Diagram
DATA-IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
2048K × 16
RAM Array
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
OE
BLE
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
20
CE
2
CE
1
Power-down
Circuit
Cypress Semiconductor Corporation
Document Number : 38-05633 Rev. *G
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 20, 2012

 
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