DATASHEET
1.5A, Radiation Hardened, Positive, High Voltage LDO
ISL75052SEH
The
ISL75052SEH
is a radiation hardened, single output LDO
specified for an output current of 1.5A. The device operates
from an input voltage range of 4.0V to 13.2V and provides for
output voltages of 0.6V to 12.7V. The output is adjustable
based on a resistor divider setting. Dropout voltages as low as
75mV (at 0.5A) typical can be realized using the device. This
allows the user to improve the system efficiency by lowering
V
IN
to nearly V
OUT
.
The ENABLE feature allows the part to be placed into a low
shutdown current mode of 165µA (typical). When enabled, the
device operates with a low ground current of 11mA (typical),
which provides for operation with low quiescent power
consumption.
The device has superior transient response and is designed
keeping single event effects in mind. This results in reduction
of the magnitude of SET seen on the output. There is no need
for additional protection diodes and filters.
A COMP pin is provided to enable the use of external
compensation. This is achieved by connecting a resistor and
capacitor from COMP to ground. The device is stable with
tantalum capacitors as low as 47µF (KEMET T525 series) and
provides excellent regulation all the way from no load to full
load. The programmable soft-start allows one to program the
inrush current by means of the decoupling capacitor used on
the BYP pin. The OCP pin allows the short-circuit output current
limit threshold to be programmed by means of a resistor from
OCP pin to GND. The OCP setting range is from a 0.16A
minimum to 3.2A maximum. The resistor sets the constant
current threshold for the output under fault conditions. The
thermal shutdown disables the output if the device
temperature exceeds the specified value. It will subsequently
enter an ON/OFF cycle until the fault is removed.
Features
• DLA SMD
5962-13220
• Input supply range 4.0V to 13.2V
• Output current up to 1.5A at T
J
= +150°C
• Best in class accuracy ±1.5%
- Over line, load and temperature
• Ultra low dropout:
- 75mV dropout (typical) at 0.5A
- 225mV dropout (typical) at 1.5A
• Noise of 100µV
RMS
(typical) between 300Hz to 300kHz
• SET mitigation with no added filtering/diodes
• Shutdown current of 165µA (typical)
• Externally adjustable output voltage
• PSRR 65dB (typical) at 1kHz
• ENable and PGood feature
• Programmable soft-start/inrush current limiting
• Adjustable overcurrent protection
• Over-temperature shutdown
• Stable with 47µF minimum tantalum capacitor
• 16 Ld flatpack package
• Radiation environment
- High dose rate (50-300rad(Si)/s) . . . . . . . . . . . 100krad(Si)
- Low dose rate (0.01rad(Si)/s) . . . . . . . . . . . . . 100krad(Si)*
- SET/SEL/SEB . . . . . . . . . . . . . . . . . . . . . . 86MeV•cm
2
/mg
*Product capability established by initial characterization. The
"EH" version is acceptance tested on a wafer-by-wafer basis to
50krad(Si) at low dose rate.
Applications
• LDO regulator for space power systems
• DSP, FPGA and µP core power supplies
• Post regulation of SMPS and down-hole drilling
Related Literature
• For a full list of related documents please visit our web page
-
ISL75052SEH
product page
EN
0.30
ISL75052SEH
3, 4, 5
200µF
0.1µF
16
8
9
10
VIN
BYP
OCP
VCCX
PG
VOUT
ADJ
EN
GND
COMP
1, 2
VIN
0.25
DROPOUT (V)
VOUT
2.5V
+150°C
+125°C
+25°C
15
14
13
12
0.20
0.15
0.10
0.05
0.1µF 200µF
15.8k
2.2k
2.2n
0.1µF
0.1µF 300
22k
VIN
22k
4.87k
1nF
0.00
PG
0
0.5
1.0
I
LOAD
(A)
1.5
2.0
FIGURE 1. TYPICAL APPLICATION
October 25, 2016
FN8456.6
FIGURE 2. DROPOUT vs I
OUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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|
Copyright Intersil Americas LLC 2013-2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL75052SEH
Block Diagram
COMP
VIN
VCCX
CURRENT
LIMIT
600mV
REFERENCE
BIAS
+
-
POWER
PDMOS
THERMAL
SHUTDOWN
ADJ
PG
-
540mV
+
DELAY
VOUT
3.8V
LDO
OCP
BYP
EN
UVLO
GND
FIGURE 3. BLOCK DIAGRAM
Typical Application
EN
ISL75052SEH
1
2
3
VIN
4
5
100µF
100µF
0.1µF
6
7
300
8
VIN
VIN
NC
NC
OCP
GND 13
COMP 12
22k
GND 11
PG 10
VOUT = 2.5V
VCCX
9
1nF
10k
PG
VCCX
VOUT
VOUT
VIN
BYP 16
ADJ 15
EN 14
0.1µF
15.8k
NC = NO CONNECT PIN CAN BE
CONNECTED TO EITHER VIN OR GND
2.2k
2.2nF
0.1µF 100µF
100µF
0.1µF
4.87k
FIGURE 4. TYPICAL APPLICATION
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FN8456.6
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ISL75052SEH
Pin Configuration
ISL75052SEH
(16 LD CDFP)
TOP VIEW
VOUT
VOUT
VIN
VIN
VIN
NC
NC
OCP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
BYP
ADJ
EN
GND
COMP
TMODE
PG
VCCX
DOTTED LINE SHOWS METAL BOTTOM
Pin Descriptions
PIN NUMBER
1, 2
3, 4, 5
6, 7
8
9
10
11
12
13
14
15
16
PIN NAME
VOUT
VIN
NC
OCP
VCCX
PG
TMODE
COMP
GND
EN
ADJ
BYP
Output voltage pins
Input supply pins
No connect. May be grounded if needed.
OCP pin allows the current limit to be programmed with an external resistor.
The 3.8V internal bus is pinned out to accept a decoupling capacitor. Connect a 0.1µF
ceramic capacitor from VCCX pin to GND.
DESCRIPTION
ESD CIRCUIT
Circuit 1
Circuit 1
Circuit 2
Circuit 2
Circuit 2
This pin is logic high when V
OUT
is in regulation signal. A logic low defines when V
OUT
is not Circuit 2
in regulation.
Test Mode pin, must be connected to GND.
Add compensation capacitor and resistor between COMP and GND.
GND pin. Pin 13 is also connected to the metal lid of the package.
V
IN
independent chip enable. TTL and CMOS compatible.
ADJ pin allows V
OUT
to be programmed with an external resistor divider.
Connect a 0.1µF capacitor from BYP pin to GND, to filter the internal VREF.
Circuit 2
Circuit 2
Circuit 2
Circuit 2
Circuit 2
Circuit 2
Circuit 2
Bottom Metalization The metal surface on the bottom surface of the package is floating. For mounting
instructions see
“Bottom Metal Mounting Guidelines” on page 15.
PAD
PAD
ESD_CL_12V
ESD_RC_7V
GND
GND
ESD CIRCUIT 1
ESD CIRCUIT 2
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FN8456.6
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ISL75052SEH
Ordering Information
ORDERING SMD NUMBER
(Note
2)
5962R1322001VXC
5962R1322001V9A
N/A
N/A
N/A
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be
used when ordering.
PART NUMBER
(Note
1)
ISL75052SEHVFE
ISL75052SEHVX
ISL75052SEHX/SAMPLE
ISL75052SEHFE/PROTO
ISL75052SEHEVAL1Z
ISL75052 SEHFE /PROTO
Evaluation Board
PART
MARKING
Q 5962R13 22001VXC
TEMP RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
(RoHS COMPLIANT)
16 Ld CDFP
Die
Die Sample
16 Ld CDFP
K16.E
PKG DWG. #
K16.E
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FN8456.6
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ISL75052SEH
Absolute Maximum Ratings
VIN Relative to GND Without Ion Beam (Note
3)
. . . . . . . . . -0.3 to +16.0V
VIN Relative to GND Under Ion Beam (Note
3)
. . . . . . . . . . . -0.3 to +14.7V
VOUT Relative to GND (Note
3)
. . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +14.7V
PG, EN, OCP/ADJ, COMP, REFIN,
REFOUT Relative to GND (Note
3).
. . . . . . . . . . . . . . . . . . -0.3 to +6.5VDC
ESD Rating
Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
16 Ld CDFP Package (Notes
6, 7)
. . . . . . .
26
4.5
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature (T
J
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Radiation Information
Maximum Total Dose
High Dose (Dose Rate = 50-300radSi/s). . . . . . . . . . . . . . . 100krads (Si)
Low Dose (Dose Rate = 10mradSi/s) (Note
5)
. . . . . . . . . . 100krads (Si)
SET (V
OUT
within ±5% During Events) . . . . . . . . . . . . . . . 86MeV•cm2/mg
SEL/B (No Latch-Up/Burnout). . . . . . . . . . . . . . . . . . . . . . 86MeV•cm2/mg
The output capacitance used for SEE testing is 2x100µF for C
IN
and C
OUT
,
100nF for BYPASS.
Recommended Operating Conditions
(Note
4)
Ambient Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Junction Temperature (T
J
) (Note
3).
. . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0V to 13.2V
VOUT Range (Note
9)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.6V to 12.7V
PG, EN, OCP/ADJ Relative to GND . . . . . . . . . . . . . . . . . . . . . . . .0V to +5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions
define limits where specifications are established.
4. Refer to
“Bottom Metal Mounting Guidelines” on page 15.
5. Product capability established by initial characterization. The “EH” version is acceptance tested on a wafer-by-wafer basis to 50krad(Si) at low dose rate.
6.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
TechBrief
TB379.
7. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
8. Electromigration specification defined as lifetime average junction temperature of +150°C where maximum rated DC current = lifetime average
current.
9. SET performance of ±5% applies to V
OUT
≥
2.5V. For V
OUT
<2.5V SEE testing will need to be performed to ensure system SET goals are met.
Electrical Specifications
Unless otherwise noted, V
IN
= V
OUT
+ 0.5V, V
OUT
= 4.0V, C
IN
= C
OUT
= 2x100µF 60mΩ, KEMET type
T541X107N025AH or equivalent, T
J
= +25°C, I
L
= 0A. Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to
“Applications Information” on page 15
and Tech Brief
TB379.
Boldface limits apply across the operating temperature range,
-55°C to +125°C. Pulse load techniques used by ATE to ensure T
J
= T
A
defines established limits.
PARAMETER
DC CHARACTERISTICS
DC Output Voltage Accuracy
V
OUT
V
OUT
Resistor adjust to: 2.5V and 5.0V
V
OUT
= 2.5V, 4.0V < V
IN
< 5.0V; 0A < I
LOAD
< 1.5A,
T
J
= -55°C to +125°C
V
OUT
= 2.5V, 4.0V < V
IN
< 5.0V; 0A < I
LOAD
< 1.5A,
T
J
= +25°C, post radiation
V
OUT
= 5.0V, 5.5V < V
IN
< 6.9V; 0A < I
LOAD
< 1.5A,
T
J
= -55°C to +125°C
V
OUT
= 5.0V, 5.5V < V
IN
< 6.9V, 0A < I
LOAD
< 1.5A,
T
J
= +25°C, post radiation
V
OUT
Resistor adjust to: 10.0V
V
OUT
= 10.0V, 10.5V < V
IN
< 13.2V, I
LOAD
= 0A,
T
J
= -55°C to +125°C
V
OUT
= 10.0V, 10.5V < V
IN
< 13.2V, I
LOAD
= 0A,
T
J
= +25°C, post radiation
V
OUT
= 10.0V, V
IN
= 10.5V, I
LOAD
= 1.5A,
V
IN
= 13.2V, I
LOAD
= 1.0A, T
J
= -55°C to +125°C
V
OUT
= 10.0V, V
IN
= 10.5V; I
LOAD
= 1.5A, V
IN
= 13.2V,
I
LOAD
= 1.0A, T
J
= +25°C, post radiation
-1.5
-2.0
-1.5
-2.0
0.2
0.2
0.2
0.2
1.5
2.0
1.5
2.0
%
%
%
%
-1.5
-2.0
-1.5
-2.0
0.2
0.2
0.2
0.2
1.5
2.0
1.5
2.0
%
%
%
%
SYMBOL
TEST CONDITIONS
MIN
(Note
10)
TYP
MAX
(Note
10)
UNIT
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FN8456.6
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