Revision 14
RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs
Radiation Performance
• SEU-Hardened Registers Eliminate the Need for Triple-Module
Redundancy (TMR)
– Immune to Single-Event Upsets (SEU) to LET
TH
> 37 MeV-
cm
2
/mg
– SEU Rate < 10
-10
Errors/Bit-Day (worst case GEO)
• SRAM Upset Rate of <10
-10
Errors/Bit-Day with Use of Error
Detection and Correction (EDAC) IP (included) with Integrated
SRAM Scrubber
– Single-Bit Correction, Double-Bit Detection
– Variable-Rate Background Refreshing
• Total Ionizing Dose Up to 300 krad (Si, Functional)
• Single-Event Latch-Up Immunity (SEL) to LET
TH
> 117 MeV-
cm
2
/mg
• TM1019 Test Data Available
Specifications
• Up to 4 Million Equivalent System Gates or 500 k Equivalent
ASIC Gates
• Up to 20,160 SEU-Hardened Flip-Flops
• Up to 840 I/Os
with
SEU-Protected Input, Output, and Enable
Registers
• Up to 540 kbits Embedded SRAM
• Manufactured on 0.15 µm CMOS Antifuse Process Technology,
7 Layers of Metal
• Electrostatic Discharge (ESD) is 2,000 V (HBM MIL-STD-883,
TM3015)
Embedded Multiply/Accumulate Blocks
(RTAX-DSP Only)
•
•
•
•
Up to 120 Multiply/Accumulate Blocks
Fully SEU- and SET-Hardened
125 MHz Performance throughout Military Temperature Range
Flexible, Cascadable Accumulate Function
Processing Flows
• B-Flow – MIL-STD-883B
• E-Flow – Extended Flow
• EV-Flow – Class V Equivalent Flow Processing Consistent with
MIL-PRF 38535
Features
• Single-Chip, Nonvolatile Solution
• 1.5 V Core Voltage for Low Power
• Flexible, Multi-Standard I/Os:
– 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation
– Bank-Selectable I/Os – 8 Banks per Chip
– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3 V PCI
– JTAG Boundary Scan Testing (as per IEEE 1149.1)
– Differential I/O Standards: LVPECL and LVDS
– Voltage-Referenced I/O Standards: GTL+, HSTL Class 1,
SSTL2 Class 1 and 2, SSTL3 Class 1 and 2
– Hot-Swap with Cold-Sparing Support (Except PCI)
• Embedded Memory with Variable Aspect Ratio:
– Independent, Width-Configurable Read and Write Ports
– Programmable Embedded FIFO Control Logic
– ROM Emulation Capability
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug Capability
Prototyping Options
• Commercial Axcelerator
®
Devices for Functional Verification
(RTAX™-S/SL only)
• RTAX-S PROTO and RTAX-DSP PROTO Devices with Same
Functional and Timing Characteristics as Flight Unit in a Non-
Hermetic Package
• Low-Priced Reprogrammable ProASIC
®
3 Option for Functional
Verification (RTAX-S/SL only)
• Offers Up To 80% Saving of Static Current Compared to
Standard RTAX-S Device at Worst-Case Conditions
RTAX-SL Low Power Option
Leading-Edge Performance
•
•
•
•
High-Performance Embedded FIFOs
350+ MHz System Performance
500+ MHz Internal Performance
700 Mb/s LVDS Capable I/Os
Table 1 • RTAX Family Product Profile
Device
Capacity
Equivalent System Gates
ASIC Gates
Modules
Register (R-cells)
Combinatorial (C-cells)
Embedded RAM/FIFO (w/o EDAC)
Core RAM Blocks
Core RAM Bits (K = 1,024)
Embedded Multiply/Accumulate
Blocks
Clocks (segmentable)
Hardwired
Routed
I/Os
I/O Banks
User I/Os (maximum)
I/O Registers
Package
CCGA/LGA*
CQFP
Note:
RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SL RTAX2000D/DL RTAX4000D/DL
250,000
30,000
1,408
2,816
12
54 k
–
1,000,000
125,000
6,048
12,096
36
162 k
–
2,000,000
250,000
10,752
21,504
64
288 k
–
4,000,000
500,000
20,160
40,320
120
540 k
–
2,000,000
250,000
9,856
19,712
64
288 k
64
4,000,000
500,000
18,480
36,960
120
540 k
120
4
4
8
198
744
624
208, 352
4
4
8
418
1,548
624
352
4
4
8
684
2,052
624, 1152
256, 352
4
4
8
840
2,520
1272
352
4
4
8
684
2,052
1272
352
4
4
8
840
2,520
1272
352
*The body size of the 1272-pin CCGA and LGA packages used on the RTAX-DSP devices is slightly larger than the body size of the 1272-
pin CCGA and LGA used on the RTAX4000S/SL devices.
October 2011
© 2011 Microsemi Corporation
i
Ordering Information
RTAX2000S
_
1
CGS
624
B
Screening Level
B = MIL-STD 883 Class B
E = E-Flow (Microsemi Space-Level Flow)
EV = Class V Equivalent Flow Processing Consistent with MIL-PRF-38535
PROTO = Prototype Unit; not for Space Flight or Qualification of Space-Flight Hardware
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack
CG = Ceramic Column Grid Array (RTAX-S/SL)
CGD = Ceramic Column Grid Array (RTAX-DSP)
LG = Land Grid Array (RTAX-S/SL)
LGD = Land Grid Array (RTAX-DSP)
S = Six Sigma Column
Speed Grade
Blank = Standard Speed
1 = Approximately 15% Faster than Standard (applies to RTAX250S/SL, RTAX1000S/SL. RTAX2000S/SL, RTAX2000D/DL FPGA Logic)
1 = Approximately 10% Faster than Standard (applies to RTAX4000S/SL, RTAX4000D/DL FPGA Logic)
Part Number
S=
SL =
D =
DL =
RTAX250S/SL
RTAX1000S/SL
RTAX2000S/SL
RTAX4000S/SL
=
=
=
=
Standard Device
Low-Power Option
DSP Device
Low-Power Option for DSP Device
250,000 Equivalent System Gates
1,000,000 Equivalent System Gates
2,000,000 Equivalent System Gates
4,000,000 Equivalent System Gates
RTAX2000D/DL = 2,000,000 Equivalent System Gates
RTAX4000D/DL = 4,000,000 Equivalent System Gates
Note:
All parts in Column Grid Array packages are now supplied with only Six Sigma solder columns.
Screening Levels
Package
CQ208
CQ256
CQ352
CG624/LG624
CG1152/LG1152
CG1272/LG1272
CGD1272/LGD1272
Note:
RTAX250S/SL
B, E, EV, PROTO
–
B, E, EV, PROTO
B, E, EV, PROTO
–
–
–
RTAX1000S/SL
–
–
B, E, EV, PROTO
B, E, EV, PROTO
–
–
–
RTAX2000S/SL RTAX4000S/SL RTAX2000D/DL RTAX4000D/DL
–
B, E, EV, PROTO
B, E, EV, PROTO
B, E, EV, PROTO
B, E, EV, PROTO
–
–
–
–
–
–
–
–
B, E, EV, PROTO
–
–
–
B, E, EV, PROTO
B, E, EV, PROTO B, E, EV, PROTO
–
–
B, E, EV, PROTO
–
–
–
–
B, E, EV, PROTO
B = MIL-STD-883 Class B
E = E-Flow (Space-Level Flow)
EV = "V" Equivalent Flow (Class V processing consistent with MIL-PRF 38535)
PROTO = Prototype unit; not for space flight or qualification of space-flight hardware.
ii
R evis i o n 14
RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs
RTAX-S/SL and RTAX-DSP Device Status
RTAX-S/SL or RTAX-DSP Device
RTAX250S
RTAX250SL
RTAX1000S
RTAX1000SL
RTAX2000S
RTAX2000SL
RTAX4000S
RTAX4000SL
RTAX2000D
RTAX4000D
RTAX2000DL
RTAX4000DL
Status
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Speed Grade and Temperature Grade Matrix
Temperature
STD
–1
RTAX250S/SL
✓
✓
RTAX1000S/SL
✓
✓
RTAX2000S/SL
✓
✓
RTAX4000S/SL
✓
✓
RTAX2000D/DL
✓
✓
RTAX4000D/DL
✓
✓
Notes:
1. Data applies to B, E, EV, and PROTO flow devices.
2. Contact your Microsemi representative for availability.
Device Resources
User I/Os (Including Clock Buffers)
Device
CQ208
CQ256
CQ352
CG624/LG624
CG1152/LG1152
CG1272/LG1272
CGD1272/LGD1272
RTAX250S/SL RTAX1000S/SL
115
–
198
232
–
–
–
–
–
198
418
–
–
–
RTAX2000S/SL
–
136
198
1
418
684
–
–
RTAX4000S/SL RTAX2000D/DL RTAX4000D/DL
–
–
166
–
–
840
–
–
–
166
1
–
–
–
684
–
–
166
–
–
–
840
2
CQ = Ceramic Quad Flat Pack, CG= Ceramic Column Grid Array, and LG = Land Grid Array
Notes:
1. RTAX2000S/SL and RTAX2000D/DL are not pin compatible in the CQ352 package type.
2. The package overhang for RTAX4000D/DL is slightly larger than RTAX4000S/SL, but they are pin compatible.
R ev i si o n 1 4
iii
I/Os per Package
Package
CQ208
CQ256
CQ352
Device
RTAX250S
RTAX2000S
RTAX250S
RTAX1000S
RTAX2000S
RTAX4000S
RTAX2000D
RTAX4000D
CG624 / LG624
RTAX250S
RTAX1000S
RTAX2000S
CG1152 / LG1152
CG1272/ LG1272
CGD1272 / LGD1272
RTAX2000S
RTAX4000S
RTAX2000D
RTAX4000D
Single-Ended
1
7
4
2
2
2
4
4
4
0
68
52
0
0
0
0
Adjacent
Differential Pairs
2
41
66
98
98
98
81
81
81
124
170
178
342
420
342
420
Non-Adjacent
Differential Pairs
3
13
0
0
0
0
0
0
0
0
5
5
0
0
0
0
Total I/Os
115
136
198
198
198
166
166
166
248
418
418
684
840
684
840
Notes:
1. Single-ended I/Os can implement only single ended I/O standards.
2. Adjacent differential pairs are pairs of I/Os that are physically adjacent and can implement differential I/O standards as well as
single-ended I/O standards.
3. Non-adjacent differential pairs are pairs of I/Os that can implement differential I/O standards as well as single-ended I/O
standards but are not physically adjacent.
4. The total number of I/Os is calculated by adding the single-ended I/Os, double the number of adjacent differential pairs, and
double the number of non-adjacent differential pairs.
iv
Revision 14
RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs
MIL-STD-883 Class B Product Flow
Table 2 • MIL-STD-883 Class B Product Flow for RTAX-S/SL and RTAX-DSP
1, 2
Step
1
2
3
4
Internal Visual
Serialization
Temperature Cycling
Constant Acceleration
1010, Condition C, 10 cycles minimum
2001, Y1 Orientation Only
Condition B for CQ256, CQ352, LG624, LG1152
Condition D for CQ208
Condition A
3
for LG1272, LGD1272, CQ352
2020, Condition A
1014
In accordance with applicable Microsemi device
specification
1015, Condition D,
160 hours at 125°C or 80 hours at 150°C minimum
In accordance with applicable Microsemi device
specification
5%
In accordance with applicable Microsemi device
specification, which includes a, b, and c:
5005, Table 1, Subgroup 1
5005, Table 1, Subgroup 2, 3
5005, Table 1, Subgroup 7
5005, Table 1, Subgroup 8a, 8b
5005, Table 1, Subgroup 9
2009
Screen
2010, Condition B
Method
Requirement
100%
100%
100%
100%
5
6
7
8
9
10
11
Particle Impact Noise Detection
Seal (Fine & Gross Leak Test)
Pre-Burn-In Electrical Parameters
Dynamic Burn-In
Interim (Post-Burn-In) Electrical Parameters
Percent Defective Allowable (PDA) Calculation
Final Electrical Test
2
a. Static Tests
(1) 25°C
(2) –55°C and +125°C
b. Functional Tests
(1) 25°C
(2) –55°C and +125°C
c. Switching Tests at 25°C
100%
100%
100%
100%
100%
All Lots
100%
12
External Visual
100%
Notes:
1. For CCGA devices, all Assembly, Screening, and TCI testing are performed at LGA level. Only QA electrical and mechanical visual are
performed after solder column attachment.
2. RTAX-S and RTAX-SL devices, as well as RTAX-D and RTAX-DL devices, have the same silicon and are distinguished by screening the ICCA
current limits at 125°C final electrical test.
3. Condition A applies to RTAX4000S/SL, RTAX2000D/DL, and RTAX4000D/DL packages only.
R ev i si o n 1 4
v
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