Maximum Junction Temperature .....................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 10 ULTRA QFN
Package Code
Outline Number
Land Pattern Number
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
JA
)
Junction to Case (θ
JC
)
110.8°C/W
62.1°C/W
V101A2CN+1
21-0610
90-0386
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages.
Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
www.maximintegrated.com
Maxim Integrated
│
2
MAX14576/MAX14636/
MAX14637
Electrical Characteristics
PARAMETER
DC CHARACTERISTICS
Supply Voltage
VBUS POR
VBUS Supply Current
VBUS Supply Current
CHARGER DETECTION
V
DP_SRC
Voltage
V
DAT_REF
Voltage
V
LGC
Voltage
I
DP_SRC
Current
CDN Pulldown Resistor
CDP Pulldown Resistor
CDP and CDN Sink Current
CDP and CDN Weak Sink
VBUS Detection Ratio
CDP and CDN Overvoltage
Comparator
Primary Detection Voltage Source
Time
t
VDP_SRC_ON
From V
VBUS
> V
VBDET
to
CHG_DET change, assuming
DCD delay = 0ms; Figure 1,
Figure 2, Figure 3
Figure 2, Figure 3
V
DP_SRC
V
DAT_REF
V
LGC
I
DP_SRC
R
DM_DWN
R
DP_DWN
I
DP_SINK
I
DM_SINK
I
WEAK
VBUS_LOW
VBUS_MID
VBUS_HIGH
V
VBUS
= 5V, no load on
CHG_DET
V
VBUS
= 5V
V
CDN
= 3.6V
I
DP_SRC
= 0 to 250µA
V
VBUS
V
VBUSUVLO
I
VBUS
I
VBUS12
V
VBUS
= 5.5V,
GOOD_BAT = 1, charger de-
tection not running
V
VBUS
= 12V, GOOD_BAT = 1,
charger detection not running
USB Charger Detectors
(V
VBUS
= 3.5V to 5.5V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
VBUS
= 5.0V, T
A
= +25°C.) (Note 2)
SYMBOL
CONDITIONS
MIN
0
1.4
2.2
150
10
TYP
MAX
28
3.15
300
16
UNITS
V
V
µA
mA
0.5
0.25
0.8
7
14.25
14.25
50
0.7
0.4
2.0
10
24.8
24.8
150
0.3
V
V
V
µA
kΩ
kΩ
µA
µA
%
22.5
42.3
76
25
47
80
4.2
46
27.5
51.7
89
V
ms
VBUS Attach to CHG_DET
t
VBUS_CHG
tG
OOD_SW
t
DCD_TMO
V
VBDET
V
VBDET_HYST
250
ms
GOOD_BAT to SW_OPEN
DCD Time Out
VBUS Detect Threshold Rising
VBUS Detect Threshold Hysteresis
USB ANALOG SWITCHES
Analog Signal Range
On-Resistance
On-Resistance Match Between
Channels
15
0.7
3.3
0.8
3.5
50
20
0.89
4
ms
s
V
mV
(Note 3, Note 4)
R
ONUSB
∆
RONUSB
I
CDP
, I
CDN
= 10mA,
V
CDP
, V
CDN
= 0 to 3V
I
CDP
, I
CDN
= 10mA,
V
CDP
, V
CDN
= 0.4V (Note 4)
0
3
V
CCINT
6
0.5
V
Ω
Ω
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Maxim Integrated
│
3
MAX14576/MAX14636/
MAX14637
Electrical Characteristics (continued)
PARAMETER
On-Resistance Flatness
Off-Leakage Current
On-Leakage Current
SYMBOL
R
FLATUSB
I
LUSB(OFF)
I
LUSB(ON)
USB Charger Detectors
(V
VBUS
= 3.5V to 5.5V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
VBUS
= 5.0V, T
A
= +25°C.) (Note 2)
CONDITIONS
I
CDP
, I
CDN
= 10mA, V
CDP
,
V
CDN
= 0 to 3.3V (Note 4)
Switch open, V
TDN
or
V
TDP
= 0.3V, 2.5V; V
CDN
or
V
CDP
= 2.5V, 0.3V
Switch closed, V
CDN
or
V
CDP
= 0.3V, 2.5V
-360
-360
MIN
TYP
0.06
MAX
0.2
360
360
UNITS
Ω
nA
nA
DIGITAL SIGNALS (GOOD_BAT, CHG_DET, SW_OPEN, CHG_AL_N)
GOOD_BAT Input Logic High
GOOD_BAT Input Logic Low
GOOD_BAT Pulldown
CHG_DET Output Logic High
CHG_DET Output Logic Low
SW_OPEN, CHG_AL_N
Output Leakage
SW_OPEN, CHG_AL_N
Output Logic Low
DYNAMIC PERFORMANCE
GOOD_BAT Debounce Time
VBUS Debounce Time
Off-Capacitance
t
GBDEB
t
CDEB
COFF
TDN, TDP applied
voltage = 0.5V
P-P
,
DC bias = 0V, f = 240MHz
CDN, CDP connected to
TDN, TDP; applied voltage =
0.5V
P-P
, DC bias = 0V,
f = 240MHz
R
L
= 50Ω, f = 20kHz, V
CDN
,
V
CDP
= 0.5V
P-P
Human Body Model
CDN, CDP
All Other Pins
IEC61000-4-2 Air-Gap
Discharge
IEC61000-4-2 Contact
Human Body Model
4
5
2
ms
ms
pF
V
IH
V
IL
R
PD
V
OH
V
OL
I
OUTLEAK
V
OL_OD
I
SOURCE
= -3mA
I
SINK
= 3mA
V
IO
= 5V, output is in high-
impedance
I
SINK
= 5mA
-1
2
1
4.36
0.4
+1
0.4
1.1
0.5
V
V
MΩ
V
V
µA
V
On-Capacitance
CONCOM
4.5
pF
Off-Isolation
ESD PROTECTION
-60
±15
±15
±8
±2
dB
kV
kV
Note 2:
All devices are 100% production tested at T
A
= +25°C. Specifications over the operating temperature range are
guaranteed by design.
Note 3:
V
CCINT
= min (V
VBUS
, +4.2V).
Note 4:
Not production tested. Guaranteed by design.
www.maximintegrated.com
Maxim Integrated
│
4
MAX14576/MAX14636/
MAX14637
USB Charger Detectors
GOOD_BAT
VBUS
CHG_AL_N
SW_OPEN
CHG_DET
CHARGER DETECTION
COMPLETED
t
VBUS_CHG
+ t
DCD_TMO
Figure 1. Normal Charger Detection (No Dead Battery)
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