Pm39F010 / Pm39F020 / Pm39F040
1 Mbit / 2 Mbit / 4 Mbit 5 Volt-only CMOS Flash Memory
FEATURES
Single Power Supply Operation
- Low voltage range: 4.5 V - 5.5 V
• Memory Organization
- Pm39F010: 128K x 8 (1 Mbit)
- Pm39F020: 256K x 8 (2 Mbit)
- Pm39F040: 512K x 8 (4 Mbit)
• High Performance Read
- 70 ns access time
• Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
- Uniform 64 Kbyte blocks (sector-group)
• Data# Polling and Toggle Bit Features
• Hardware Data Protection
• Automatic Erase and Byte Program
-
Typical 16 µs/byte programming time
- Typical 55 ms sector/block/chip erase time
• Low Power Consumption
- Typical 8 mA active read current
- Typical 9 mA program/erase current
- Typical 0.5 µA CMOS standby current
• High Product Endurance
- Guarantee 100,000 program/erase cycles per
single sector (preliminary)
- Minimum 20 years data retention
• Industrial Standard Pin-out and Packaging
- 32-pin PLCC
- 32-pin VSOP (TSOP 8mm x 14mm)
- Optional lead-free (Pb-free) packages
GENERAL DESCRIPTION
The Pm39F010/020/040 are 1 Mbit/2 Mbit/4 Mbit 5.0 Volt-only Flash Memories. These devices are designed to use
a single low voltage, range from 4.5 Volt to 5.5 Volt, power supply to perform read, erase and program operations.
The 12.0 Volt V
PP
power supply for program and erase operations are not required. The devices can be programmed
in standard EPROM programmers as well.
The memory arrays of Pm39F010/020/040 are divided into uniform 4 Kbyte sectors or uniform 64 Kbyte blocks
(sector group - consists of sixteen adjacent sectors). The sector or block erase feature allows users to flexibly
erase an memory area as small as 4 Kbyte or as large as 64 Kbyte by one single erase operation without affecting
the data in others. The chip erase feature allows the whole memory array to be erased in one single erase opera-
tion. The devices can be programmed on a byte-by-byte basis after performing the erase operation.
The devices have a standard microprocessor interface as well as a JEDEC standard pin-out/command set. The
program operation is executed by issuing the program command code into command register. The internal control
logic automatically handles the programming voltage ramp-up and timing. The erase operation is executed by
issuing the chip erase, block, or sector erase command code into command register. The internal control logic
automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been
programmed is not required before an erase operation. The devices offer Data# Polling and Toggle Bit functions, the
progress or completion of program and erase operations can be detected by reading the Data# Polling on I/O7 or
the Toggle Bit on I/O6.
The Pm39F010/020/040 are manufactured on pFLASH™’s advanced nonvolatile CMOS technology. The devices
are offered in 32-pin PLCC and VSOP packages with access time 70 ns.
Chingis Technology Corporation
1
Issue Date: April, 2006, Rev:1.5
Pm39F010 / Pm39F020 / Pm39F040
PIN DESCRIPTIONS
SYMBOL
A0 - A
MS(1)
TYPE
INPUT
DESCRIPTION
Address Inputs: For memory addresses input. Addresses are internally
latched on the falling edge of WE# during a write cycle.
Chip Enable: CE# goes low activates the device's internal circuitries for
device operation. CE# goes high deselects the device and switches into
standby mode to reduce the power consumption.
Write Enable: Activate the device for write operation. WE# is active low.
Output Enable: Control the device's output buffers during a read cycle. OE#
is active low.
Data Inputs/Outputs: Input command/data during a write cycle or output data
during a read cycle. The I/O pins float to tri-state when OE# are disabled.
Device Power Supply
Ground
No Connection
CE#
INPUT
WE#
OE#
I/O0 - I/O7
V
CC
GND
NC
INPUT
INPUT
INPUT/
OUTPUT
Note:
1. A
MS
is the most significant address where A
MS
= A16 for Pm39F010, A17 for Pm39F020, and A18 for
Pm39F040.
Chingis Technology Corporation
5
Issue Date: April, 2006, Rev: 1.5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
