BM6103FV-C
Datasheet
Gate Driver Providing Galvanic isolation Series
Isolation voltage 2500Vrms
1ch Gate Driver Providing Galvanic Isolation
BM6103FV-C
●General
Description
The BM6103FV-C is a gate driver with isolation voltage
2500Vrms, I/O delay time of 350ns, and minimum input
pulse width of 180ns, and incorporates the fault signal
output functions, undervoltage lockout (UVLO) function,
thermal protection function, and short current protection
(SCP, DESAT) function.
●Features
Providing Galvanic Isolation
Active Miller Clamping
Fault signal output function
(Adjustable output holding time)
Undervoltage lockout function
Thermal protection function
Short current protection function
(Adjustable reset time)
Soft turn-off function for short current protection
(Adjustable turn-off time)
Supporting Negative VEE2
●Key
Specifications
Isolation voltage:
Maximum gate drive voltage:
I/O delay time:
Minimum input pulse width:
●Package
SSOP-B20W
2500Vrms
24V
350ns(Max.)
180ns(Max.)
W(Typ.) x D(Typ.) x H(Max.)
6.50mm x 8.10mm x 2.01mm
●Applications
■
Automotive isolated IGBT/MOSFET inverter gate drive
■
Automotive DC-DC converter
■
Industrial inverters system
■
UPS system
●Typical
Application Circuits
GND1
PROOUT
LOGIC
MASK
FLTRLS
VCC1
FLT
UVLO
MASK
FB
TIMER
LOGIC
VEE2
R
FLT RLS
NC
INB
S
Q
R
PRE
DRIVER
VEE2
OUT1
VCC2
UVLO
MASK
OUT2
SCPIN
GND2
VEE2
VTSIN
ECU
C
FLT RLS
C
VCC1
INA
ENA
TEST
MASK
GND1
FLT
TIMER
FLT
MASK
MASK
Input side
chip
Output side
chip
Temp Sensor
Figure 1. For using 4-pin IGBT (for using SCP function)
GND1
PROOUT
LOGIC
MASK
S
Q
R
VCC2
LOGIC
FB
TIMER
PRE
DRIVER
VEE2
OUT1
R
FLT RLS
NC
INB
FLTRLS
VCC1
FLT
UVLO
MASK
UVLO
MASK
OUT2
SCPIN
GND2
VEE2
VTSIN
ECU
C
FLT RLS
C
VCC1
INA
ENA
TEST
GND1
MASK
FLT
TIMER
FLT
MASK
MASK
Input side
chip
Output side
chip
Temp Sensor
Figure 2. For using 3-pin IGBT (for using DESAT function)
○Product
structure：Silicon integrated circuit
.
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© 2012 ROHM Co., Ltd. All rights reserved.
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○This
product is not designed protection against radioactive rays
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C
VCC2
VEE2
VREG
C
VCC2
VREG
BM6103FV-C
●Recommended
range of external constants
Pin Name
FLTRLS
VREG
VCC1
VCC2
●Pin
Configuration
SSOP-B20W
(TOP VIEW)
Symbol
C
FLTRLS
R
FLTRLS
C
VREG
C
VCC1
C
VCC2
Recommended Value
Min.
-
50
1.0
0.1
0.33
Typ.
0.01
200
3.3
1.0
-
Max.
0.47
1000
10.0
-
-
Unit
uF
kΩ
uF
uF
uF
Datasheet
Figure 3. Pin configuration
●Pin
Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
VTSIN
VEE2
GND2
SCPIN
OUT2
VREG
VCC2
OUT1
VEE2
PROOUT
GND1
NC
INB
FLTRLS
VCC1
FLT
INA
ENA
TEST
GND1
Thermal detection pin
Output-side negative power supply pin
Output-side ground pin
Short current detection pin
MOS FET control pin for Miller Clamp
Power supply pin for driving MOS FET for Miller Clamp
Output-side positive power supply pin
Output pin
Output-side negative power supply pin
Soft turn-off pin
Input-side ground pin
No Connect
Invert / non-invert selection pin
Fault output holding time setting pin
Input-side power supply pin
Fault output pin
Control input pin
Input enabling signal input pin
Test mode setting pin
Input-side ground pin
Function
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BM6103FV-C
Datasheet
●Description
of pins and cautions on layout of board
1) VCC1 (Input-side power supply pin)
The VCC1 pin is a power supply pin on the input side. To suppress voltage fluctuations due to the current to drive
internal transformers, connect a bypass capacitor between the VCC1 and the GND1 pins.
2) GND1 (Input-side ground pin)
The GND1 pin is a ground pin on the input side.
3) VCC2 (Output-side positive power supply pin)
The VCC2 pin is a positive power supply pin on the output side. To reduce voltage fluctuations due to OUT1 pin output
current and due to the current to drive internal transformers, connect a bypass capacitor between the VCC2 and the
GND2 pins.
4) VEE2 (Output-side negative power supply pin)
The VEE2 pin is a power supply pin on the output side. To suppress voltage fluctuations due to OUT1 pin output current and
due to the current to drive internal transformers, connect a bypass capacitor between the VEE2 and the GND2 pins. To use
no negative power supply, connect the VEE2 pin to the GND2 pin.
5) GND2 (Output-side ground pin)
The GND2 pin is a ground pin on the output side. Connect the GND2 pin to the emitter / source of a power device.
6) IN (Control input terminal)
The IN pin is a pin used to determine output logic.
ENA
INB
INA
H
X
X
L
L
L
L
L
H
L
H
L
L
H
H
OUT1
L
L
H
H
L
7) FLT (Fault output pin)
The FLT pin is an open drain pin used to output a fault signal when a fault occurs (i.e., when the undervoltage lockout
function (UVLO), short current protection function (SCP) or thermal protection function is activated).
This pin is I/O pin and if L voltage is externally input, the output is set to L status regardless of other input logic.
Consequently, be sure to connect the pull-up resistor between VCC1 pin and the FLT pin even if this pin is not used.
Pin
FLT
While in normal operation
Hi-Z
When an Fault occurs
L
(When UVLO, SCP or thermal protection is activated)
8) FLTRLS (Fault output holding time setting pin)
The FLTRLS pin is a pin used to make setting of time to hold a Fault signal. Connect a capacitor between the FLTRLS
pin and the GND1 pin, and a resistor between it and the VCC1 pin.
The Fault signal is held until the FLTRLS pin voltage exceeds a voltage set with the V
FLTRLS
parameter. To set holding
time to 0 ms, do not connect the capacitor. Short-circuiting the FLTRLS pin to the VCC1 pin will cause a high current to
flow in the FLTRLS pin and, in an open state, may cause the IC to malfunction. To avoid such trouble, be sure to connect
a resistor between the FLTRLS and the VCC1 pins.
9) OUT1 (Output pin)
The OUT1 pin is a pin used to drive the gate of a power device.
10) OUT2 (MOS FET control pin for Miller Clamp)
The OUT2 pin is a pin for controlling the external MOS switch for preventing increase in gate voltage due to the miller
current of the power device connected to OUT1 pin.
11) VREG (Power supply pin for driving MOS FET for Miller Clamp)
The VREG pin is a power supply pin for driving MOS FET for Miller Clamp. Be sure to connect a capacitor between
VREG pin and VEE2 pin for preventing the oscillation and to reduce voltage fluctuations due to OUT2 pin output current.
12) PROOUT (Soft turn-off pin)
The PROOUT pin is a pin used to put the soft turn-off function of a power devise in operation when the SCP function is
activated. This pin combines with the gate voltage monitoring pin for Miller Clamp.
13) SCPIN (Short current detection pin)
The SCPIN pin is a pin used to detect current for short current protection. When the SCPIN pin voltage exceeds a
voltage set with the V
SCDET
parameter, the SCP function will be activated. This may cause the IC to malfunction in an
open state. To avoid such trouble, short-circuit the SCPIN pin to the GND2 pin if the short current protection is not used.
In order to prevent the wrong detection due to noise, the noise mask time t
SCPMSK
is set.
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BM6103FV-C
Datasheet
14) VTSIN (Thermal detection pin)
The VTSIN pin is a temperature sensor voltage input pin, which can be used for thermal protection of an output device.
If VTSIN pin voltage becomes V
TSDET
or less, OUT pin is set to L. In the open status, the IC may malfunction, so be sure
to supply the VTSPIN more than V
TSDET
if the thermal protection function is not used. In order to prevent the wrong
detection due to noise, the noise mask time t
TSMSK
is set.
●Description
of functions and examples of constant setting
1) Miller Clamp function
When OUT1=L and PROOUT pin voltage < V
OUT2ON
, H is output from OUT2 pin and the external MOS switch is turned
ON. When OUT1=H, L is output from OUT2 pin and the external MOS switch is turned OFF. While the short-circuit
protection function is activated, L is output from OUT2 pin and the external MOS switch is turned OFF.
Short current
Detected
SCPIN
Not less than
V
SCDET
X
Not detected
X
X
IN
X
L
L
H
PROOUT
X
Not less than V
OUT2ON
Not more than V
OUT2ON
X
OUT2
L
Hi-Z
H
L
VCC2
PREDRIV ER
PREDRIV ER
PROOUT
LOGIC
PREDRIV ER
REGULATOR
PREDRIV ER
PREDRIV ER
-
+
OUT1
VREG
OUT2
V
OUT2ON
GND2
VEE2
Figure 4. Block diagram of Miller Clamp function
t
POFF
t
PON
IN
OUT1
PROOUT
(Monitor the gate voltage)
t
OUT2ON
OUT2
Figure 5. Timing chart of Miller Clamp function
V
OUT2ON
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BM6103FV-C
Datasheet
2) Fault status output
This function is used to output a fault signal from the FLT pin when a fault occurs (i.e., when the undervoltage lockout
function (UVLO), short current protection function (SCP) or thermal protection function is activated) and hold the Fault
signal until the set Fault output holding time is completed. The Fault output holding time t
FLTRLS
is given as the following
equation with the settings of capacitor C
FLTRLS
and resistor R
FLTRLS
connected to the FLTRLS pin. For example, when
C
FLTRLS
is set to 0.01
F and R
FLTRLS
is set to 200k, the holding time will be set to 2 ms.
t
FLTRLS
[ms]= C
FLTRLS
[
F]•R
FLTRLS
[k]
To set the fault output holding time to “0” ms, only connect the resistor R
FLTRLS
.
Status
Normal
Fault occurs
FLT pin
Hi-Z
L
Status
Fault occurs
(The UVLO, SCP or thermal protection)
UVLO
SCP
VTS
VCC1
V
FLTRLS
MASK
MASK
MASK
FLT
S
R
Hi-Z
FLT
L
H
OUT
L
C
FLTRLS
R
FLTRLS
FLTRLS
FLTRLS
+
-
FLT
MASK
ECU
Fault output holding time (t
FLTRLS
)
Figure 6. Fault Status Output Timing Chart
LOGIC
GND1
Figure 7. Fault Output Block Diagram
3) Undervoltage Lockout (UVLO) function
The BM6103FV-C incorporates the undervoltage lockout (UVLO) function both on the low and the high voltage sides.
When the power supply voltage drops to the UVLO ON voltage, the OUT pin and the FLT pin both will output the “L”
signal. When the power supply voltage rises to the UVLO OFF voltage, these pins will be reset. However, during the fault
output holding time set in “2) Fault status output” section, the OUT pin and the FLT pin will hold the “L” signal. In addition,
to prevent malfunctions due to noises, mask time t
UVLO1MSK
and t
UVLO2MSK
are set on both low and high voltage sides.
IN
H
L
V
UVLO1H
V
UVLO1L
VCC1
FLT
OUT1
Figure 8. Input-side UVLO Function Operation Timing Chart
IN
Hi-Z
L
H
L
H
L
V
UVLO2H
V
UVLO2L
VCC2
FLT
OUT1
Figure 9. Output-side UVLO Operation Timing Chart
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© 2012 ROHM Co., Ltd. All rights reserved.
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Hi-Z
L
H
Hi-Z
L
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