and eight bidirectional data lines, DQ(7:0). The E Device Enable
controls device selection, active, and standby modes. Asserting
E enables the device, causes I
DD
to rise to its active value, and
decodes the 19 address inputs to select one of 524,288 words in
the memory. W controls read and write operations. During a
read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
X
1
W
X
0
1
1
E
1
0
0
0
I/O Mode
3-state
Data in
3-state
Data out
Mode
Standby
Write
Read
2
Read
A18
A16
A14
A12
A7
A6
A5
A4
V
D D
V
SS
A3
A2
A1
A0
DQ0
DQ1
DQ2
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A15
A17
W
A13
A8
A9
A11
V
S S
V
D D
G
A10
E
DQ7
DQ6
DQ5
DQ4
NC
X
1
0
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than V
IH
(min), G and E less than
V
IL
(max) defines a read cycle. Read access time is measured
from the latter of Device Enable, Output Enable, or valid address
to valid data output.
SRAM read Cycle 1, the Address Access in figure 3a, is initiated
by a change in address inputs while the chip is enabled with G
asserted and W deasserted. Valid data appears on data outputs
DQ(7:0) after the specified t
AVQV
is satisfied. Outputs remain
active throughout the entire cycle. As long as Device Enable and
Output Enable are active, the address inputs may change at a
rate equal to the minimum read cycle time (t
AVAV
).
SRAM read Cycle 2, the Chip Enable-Controlled Access in
figure 3b, is initiated by E going active while G remains asserted,
W remains deasserted, and the addresses remain stable for the
entire cycle. After the specified t
ETQV
is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable-Controlled Access in
figure 3c, is initiated by G going active while E is asserted, W
is deasserted, and the addresses are stable. Read access time is
t
GLQV
unless t
AVQV
or t
ETQV
have not been satisfied.
Figure 2a. UT7Q512 100ns SRAM Shielded
Package Pinout (36)
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
D D
A15
A17
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Figure 2b. UT7Q512 100ns SRAM
Package Pinout (32)
2
WRITE CYCLE
A combination of W less than V
IL
(max) and E less than
V
IL
(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than V
IH
(min), or when W is less
than V
IL
(max).
Write Cycle 1, the Write Enable-Controlled A ccess in figure 4a,
is defined by a write terminated by W going high, with E still
active. The write pulse width is defined by t
WLWH
when the
write is initiated by W, and by t
ETWH
when the write is initiated
by E. Unless the outputs have been previously placed in the high-
impedance state byG, the user must wait t
WLQZ
before applying
data to the nine bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-Controlled Access in figure 4b,
is defined by a write terminated by the latter of E going inactive.
The write pulse width is defined by t
WLEF
when the write is
initiated by W, and by t
ETEF
when the write is initiated by the
E going active. For the W initiated write, unless the outputs have
been previously placed in the high-impedance state
by G, the user must wait t
WLQZ
before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
Table 2. Typical Radiation Hardness
Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
30
1.5E-7
krad(Si) nominal
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 9 0% worst case particle environment, Geosynchronous orbit, 100 m ils of
Aluminum.
3
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.5 to 7.0V
-0.5 to 7.0V
-65 to +150°C
1.0W
+150°C
10°C/W
±
10 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
4.5 to 5.5V
-55 to +125°C
0V to V
DD
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(V
DD
= 5.0V±10%) (-55°C to +125°C)
SYMBOL
V
IH
V
IL
V
OL
V
OH
C
IN 1
C
IO 1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage current
I
OL
= 2.1mA,V
DD
=4.5V
I
OH
= -1mA,V
DD
=4.5V
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
V
SS
< V
IN
< V
DD
, V
DD
= V
DD
(max)
0V < V
O
< V
DD
V
DD
= V
DD
(max)
G = V
DD
(max)
I
OS 2, 3
I
DD
(OP)
Short-circuit output current
Supply current operating
@ 1MHz
0V <V
O
<V
DD
Inputs: V
IL
= V
SS
+ 0.8V,
V
IH
= 2.2V
I
OUT
= 0mA
V
DD
= V
DD
(max)
I
DD1
(OP)
Supply current operating
@10MHz
Inputs: V
IL
= V
SS
+ 0.8V,
V
IH
= 2.2V
I
OUT
= 0mA
V
DD
= V
DD
(max)
I
DD2
(SB)
Nominal standby supply current
@0MHz
Inputs: V
IL
= V
SS
I
OUT
= 0mA
E = V
DD
- 0.5
V
DD
= V
DD
(max)
V
IH
= V
DD
- 0.5V
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 .
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
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