NCV8873
Automotive Grade
Non-Synchronous Boost
Controller
The NCV8873 is an adjustable output non−synchronous boost
controller which drives an external N−channel MOSFET. The device
uses peak current mode control with internal slope compensation. The
IC incorporates an internal regulator that supplies charge to the gate
driver.
Protection features include internally−set soft−start, undervoltage
lockout, cycle−by−cycle current limiting and thermal shutdown.
Additional features include low quiescent current sleep mode and
externally−synchronizable switching frequency.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
8873xx = Specific Device Code
xx = 00
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
8873xx
ALYW
G
•
•
•
•
•
•
•
•
•
•
•
Peak Current Mode Control with Internal Slope Compensation
0.2 V
$3%
Reference Voltage for Constant Current Loads
Fixed Frequency Operation
Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump
Input Undervoltage Lockout (UVLO)
Internal Soft−Start
Low Quiescent Current in Sleep Mode
Cycle−by−Cycle Current Limit Protection
Hiccup−Mode Overcurrent Protection (OCP)
Thermal Shutdown (TSD)
This is a Pb−Free Device
PIN CONNECTIONS
EN/SYNC 1
ISNS 2
GND 3
GDRV 4
(Top View)
8 VFB
7 VC
6 VIN
5 VDRV
ORDERING INFORMATION
Device
NCV887300D1R2G
Package
SOIC−8
(Pb−Free)
Shipping
†
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2012
May, 2012
−
Rev. 2
1
Publication Order Number:
NCV8873/D
NCV8873
VIN
C
DRV
VDRV
GDRV
ISNS
GND
R
SNS
Dn
VFB
R
F1
V
ref
L
D1
V
o
Q
D2
C
o
C
g
V
g
TEMP
FAULT
LOGIC
EN/
SYNC
EN/SYNC
1
OSC
PWM
SC
VC
R
C
C
C
Gm
SS
CLK
DRIVE
LOGIC
CSA
VDRV
6
5
4
2
3
CL
+
7
8
Figure 1. Simplified Block Diagram and Application Schematic
PACKAGE PIN DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
Pin
Symbol
EN/SYNC
ISNS
GND
GDRV
VDRV
VIN
VC
VFB
Function
Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled
into sleep mode when this pin is brought low for longer than the enable time−out period.
Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense
resistor to ground to sense the switching current for regulation and current limiting.
Ground reference.
Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from
GDRV to the gate to tailor EMC performance.
Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass
with a 1.0
mF
ceramic capacitor to ground.
Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi-
tion to a diode from the output voltage to VDRV and/or VIN.
Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize
the converter.
Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND
creates a voltage divider for regulation and programming of the output voltage.
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NCV8873
ABSOLUTE MAXIMUM RATINGS
(Voltages are with respect to GND, unless otherwise indicated)
Rating
Dc Supply Voltage (VIN)
Peak Transient Voltage (Load Dump on VIN)
Dc Supply Voltage (VDRV, GDRV)
Peak Transient Voltage (VFB)
Dc Voltage (VC, VFB, ISNS)
Dc Voltage (EN/SYNC)
Dc Voltage Stress (VIN
−
VDRV)*
Operating Junction Temperature
Storage Temperature Range
Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C
Value
−0.3
to 40
45
12
−0.3
to 6
−0.3
to 3.6
−0.3
to 6
−0.7
to 40
−40
to 150
−65
to 150
265 peak
Unit
V
V
V
V
V
V
V
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage.
PACKAGE CAPABILITIES
Characteristic
ESD Capability (All Pins)
Moisture Sensitivity Level
Package Thermal Resistance
1. 1 in
2
, 1 oz copper area used for heatsinking.
Junction−to−Ambient, R
qJA
(Note 1)
Human Body Model
Machine Model
Value
w2.0
w200
1
100
°C/W
Unit
KV
V
Ordering Options
The NCV8873 features several variants to better fit a
multitude of applications. The table below shows the typical
TYPICAL VALUES
YY
NCV887300
D
max
86.5%
f
s
1000 kHz
t
ss
1.6 ms
S
a
values of parameters for the parts that are currently
available.
V
cl
400 mV
I
src
800 mA
I
sink
600 mA
V
DRV
6.3 V
130 mV/ms
DEFINITIONS
Symbol
D
max
S
a
I
sink
Characteristic
Maximum duty cycle
Slope compensating ramp
Gate drive sinking current
Symbol
f
s
V
cl
V
DRV
Characteristic
Switching frequency
Current limit trip voltage
Drive voltage
Symbol
t
ss
I
src
Characteristic
Soft−start time
Gate drive sourcing current
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NCV8873
ELECTRICAL CHARACTERISTICS
(−40°C < T
J
< 150°C, 3.2 V < V
IN
< 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
GENERAL
Quiescent Current, Sleep Mode
Quiescent Current, Sleep Mode
Quiescent Current, No switching
Quiescent Current, Switching,
normal operation
OSCILLATOR
Minimum pulse width
Maximum duty cycle
Switching frequency
Soft−start time
t
on,min
D
max
f
s
t
ss
YY = 00
YY = 00
From start of switching with V
FB
= 0 until
reference voltage = V
REF
YY = 00
From EN
→
1 until start of switching with
V
FB
= 0
YY = 00
90
84
900
115
86.5
1000
140
89
1100
ns
%
kHz
ms
1.3
−
114
1.6
240
130
1.9
280
146
ms
mV/ms
I
q,sleep
I
q,sleep
I
q,off
I
q,on
V
IN
= 13.2 V, EN = 0, T
J
= 25°C
V
IN
= 13.2 V, EN = 0,
−40°C
< T
J
< 125°C
Into VIN pin, EN = 1, No switching
Into VIN pin, EN = 1, Switching
−
−
−
−
2.0
2.0
1.5
4.0
−
6.0
2.5
6.0
mA
mA
mA
mA
Symbol
Conditions
Min
Typ
Max
Unit
Soft−start delay
Slope compensating ramp
ENABLE/SYNCHRONIZATION
EN/SYNC pull−down current
EN/SYNC input high voltage
EN/SYNC input low voltage
EN/SYNC time−out ratio
t
ss,dly
S
a
I
EN/SYNC
V
s,ih
V
s,il
%t
en
V
EN/SYNC
= 5 V
−
2.0
0
5.0
−
−
−
10
5.0
800
350
mA
V
mV
%
From SYNC falling edge, to oscillator con-
trol (EN high) or shutdown (EN low), Per-
cent of typical switching frequency
Percent of f
s
From SYNC falling edge to GDRV falling
edge
−
SYNC minimum frequency ratio
SYNC maximum frequency
Synchronization delay
Synchronization duty cycle
CURRENT SENSE AMPLIFIER
Low−frequency gain
Bandwidth
ISNS input bias current
Current limit threshold voltage
Current limit,
Response time
Overcurrent protection,
Threshold voltage
Overcurrent protection,
Response Time
%f
sync,min
f
sync,max
t
s,dly
D
sync
A
csa
BW
csa
I
sns,bias
V
cl
t
cl
%V
ocp
t
ocp
−
1.1
−
25
−
−
50
−
80
−
100
75
%
MHz
ns
%
Input−to−output gain at dc, ISNS
v
1 V
Gain of A
csa
−
3 dB
Out of ISNS pin
Voltage on ISNS pin
YY = 00
CL tripped until GDRV falling edge,
V
ISNS
= V
cl
+ 40 mV
Percent of V
cl
From overcurrent event, Until switching
stops, V
ISNS
= V
OCP
+ 40 mV
0.9
2.5
−
360
−
125
−
1.0
−
30
400
80
150
80
1.1
−
50
440
125
175
125
V/V
MHz
mA
mV
ns
%
ns
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NCV8873
ELECTRICAL CHARACTERISTICS
(−40°C < T
J
< 150°C, 3.2 V < V
IN
< 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
Transconductance
VEA output resistance
VFB input bias current
Reference voltage
VEA maximum output voltage
VEA minimum output voltage
VEA sourcing current
VEA sinking current
GATE DRIVER
Sourcing current
Sinking current
Driving voltage dropout
Driving voltage source current
Backdrive diode voltage drop
Driving voltage
UVLO
Undervoltage lock−out,
Threshold voltage
Undervoltage lock−out,
Hysteresis
THERMAL SHUTDOWN
Thermal shutdown threshold
Thermal shutdown hysteresis
Thermal shutdown delay
T
sd
T
sd,hys
t
sd,dly
T
J
rising
T
J
falling
From T
J
> T
sd
to stop switching
160
10
−
170
15
−
180
20
100
°C
°C
ns
V
uvlo
V
uvlo,hys
V
IN
falling
V
IN
rising
2.95
50
3.05
150
3.15
250
V
mV
I
src
I
sink
V
drv,do
I
drv
V
d,bd
V
DRV
V
DRV
≥
6 V, V
DRV
−
V
GDRV
= 2 V
YY = 00
V
GDRV
≥
2 V
YY = 00
V
IN
−
V
DRV
, Iv
DRV
= 25 mA
V
IN
−
V
DRV
= 1 V
V
DRV
−
V
IN
, I
d,bd
= 5 mA
I
VDRV
= 0.1
−
25 mA
YY = 00
600
500
−
35
−
6.0
800
600
0.3
45
−
6.3
−
−
0.6
−
0.7
6.6
mA
mA
V
mA
V
V
g
m,vea
R
o,vea
I
vfb,bias
V
ref
V
c,max
V
c,min
I
src,vea
I
snk,vea
VEA output current, Vc = 2.0 V
VEA output current, Vc = 0.7 V
Current out of VFB pin
V
FB
– V
ref
=
±
20 mV
0.8
2.0
−
0.194
2.5
−
80
80
1.2
−
0.5
0.200
−
−
100
100
1.5
−
2.0
0.206
−
0.3
−
−
mS
MW
mA
V
V
V
mA
mA
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