CY7C4221 CY7C42311 K / 2 K × 9 Synchronous FIFOs
CY7C4221 / CY7C4231
1 K / 2 K × 9 Synchronous FIFOs
1 K / 2 K × 9 Synchronous FIFOs
Features
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Functional Description
The CY7C42X1 are high-speed, low-power FIFO memories with
clocked read and write interfaces. All are nine bits wide. The
CY7C42X1 are pin-compatible to IDT722X1. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor interfaces,
and communications buffering.
These FIFOs have 9-bit input and output ports that are controlled
by separate clock and enable signals. The input port is controlled
by a free-running clock (WCLK) and two write-enable pins
(WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written into
the FIFO on the rising edge of the WCLK signal. While WEN1,
WEN2/LD is held active, data is continually written into the FIFO
on each WCLK cycle. The output port is controlled in a similar
manner by a free-running read clock (RCLK) and two
read-enable pins (REN1, REN2). In addition, the CY7C42X1 has
an output enable pin (OE). The Read (RCLK) and Write (WCLK)
clocks can be tied together for single-clock operation or the two
clocks can run independently for asynchronous read/write
applications. Clock frequencies up to 100 MHz are achievable.
Depth expansion is possible using one enable input for system
control, while the other enable is controlled by expansion logic to
direct the flow of data.The CY7C42X1 provides four status pins:
Empty, Full, Almost Empty, Almost Full. The Almost
Empty/Almost Full flags are programmable to single word
granularity. The programmable flags default to Empty – 7 and
Full – 7.
The flags are synchronous, they change state relative to either
the Read clock (RCLK) or the Write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the flags
are updated exclusively by the RCLK. The flags denoting Almost
Full and Full states are updated exclusively by WCLK. The
synchronous flag architecture guarantees that the flags maintain
their status for at least one cycle.
All configurations are fabricated using advanced 0.65
N-Well
CMOS technology. Input ESD protection is greater than 2001 V,
and latch up is prevented by the use of guard rings.
High-speed, low-power, first-in first-out (FIFO) memories
❐
1 K × 9 (CY7C4221)
❐
2 K × 9 (CY7C4231)
High-speed 66.7 MHz operation (15 ns read/write cycle time)
Low power (I
CC
= 35 mA)
Fully asynchronous and simultaneous read and write operation
Empty, Full, and Programmable Almost Empty and Almost Full
status flags
TTL-compatible
Output Enable (OE) pin to three-state the output bus
Independent read and write enable pins
Center power and ground pins for reduced noise
Width-expansion capability
Space saving 7 mm × 7 mm 32-pin TQFP and 32-pin PLCC
packages available
Pin-compatible and functionally equivalent to IDT72221 &
72231
Pb-free packages available
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Cypress Semiconductor Corporation
Document Number: 38-06016 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 17, 2012
CY7C4221 / CY7C4231
Selection Guide
Description
Maximum frequency
Maximum access time
Minimum cycle time
Minimum data or enable setup
Minimum data or enable hold
Maximum flag delay
Active power supply current
Commercial
Industrial
-15
66.7
10
15
4
1
10
35
40
Unit
MHz
ns
ns
ns
ns
ns
mA
CY7C4221
Density
1K×9
CY7C4231
2K×9
Logic Block Diagram
D0 - 8
INPUT
REGISTER
WCLK WEN1 WEN2/LD
FLAG
PROGRAM
REGISTER
Write
CONTROL
FLAG
LOGIC
Dual Port
RAM Array
1K x 9
Write
POINTER
2Kx 9
Read
POINTER
EF
PAE
PAF
FF
RS
RESET
LOGIC
THREE-ST
ATE
OUTPUT REGISTER
OE
Q0 - 8
Read
CONTROL
RCLK REN1 REN2
Document Number: 38-06016 Rev. *H
Page 2 of 22
CY7C4221 / CY7C4231
Contents
Pin Configuration ............................................................. 4
Pin Definitions .................................................................. 4
Architecture ...................................................................... 5
Resetting the FIFO ............................................................ 5
FIFO Operation ................................................................. 5
Programming .................................................................... 5
Programmable Flag (PAE, PAF) Operation ................ 6
Width Expansion Configuration ...................................... 7
Flag Operation .................................................................. 7
Full Flag ....................................................................... 7
Empty Flag .................................................................. 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
Electrical Characteristics ................................................. 8
Capacitance ...................................................................... 8
AC Test Loads and Waveforms ....................................... 9
Switching Characteristics ................................................ 9
Switching Waveforms .................................................... 10
Typical AC and DC Characteristics .............................. 16
Ordering Information ...................................................... 17
1 K × 9 Synchronous FIFO ........................................ 17
2 K × 9 Synchronous FIFO ........................................ 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Document Number: 38-06016 Rev. *H
Page 3 of 22
CY7C4221 / CY7C4231
Pin Configuration
Figure 1. Pin Diagram
PLCC
Top View
D
2
RS
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
OE
EF
FF
Q
0
Q
1
Q
2
Q
3
Q
4
4 3 2 1 32 3130
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12
22
21
13
14151617181920
EF
FF
Q
0
Q
1
Q
2
Q
3
Q
4
TQFP
Top View
D
3
D
4
D
5
D
6
D
7
D
8
RS
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
OE
D
2
D
3
D
4
D
5
D
6
D
7
D
8
32 31 30 29 28 27 26 25
D
1
D
0
PAF
PAE
GND
REN1
RCLK
REN2
24
23
22
21
20
19
18
17
WEN1
WCLK
WEN2/LD
V
CC
Q
8
Q
7
Q
6
Q
5
Pin Definitions
Pin
D
0–8
Q
0–8
WEN1
Name
Data Inputs
Data Outputs
Write Enable 1
I/O
I
I
Data inputs for 9-bit bus.
The only write enable to have programmable flags when device is configured. Data is written on
a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is
configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when
WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin operates as
a control to write or read the programmable flag offsets. WEN1 must be LOW and WEN2 must be
HIGH to write data into the FIFO. Data is not written into the FIFO if the FF is LOW. If the FIFO is
configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable
flag offsets.
Enables device for read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW, WEN2/LD is HIGH, and the FIFO
is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO is not
Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset register.
O Data outputs for 9-bit bus.
Description
WEN2/LD Write Enable 2
Dual Mode
Load
Pin
I
I
REN1,
REN2
WCLK
RCLK
EF
FF
PAE
PAF
RS
OE
Read Enable
Inputs
Write Clock
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Reset
Output Enable
I
I
I
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed
into the FIFO.
O When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into
the FIFO.
I
I
Resets device to empty condition. A reset is required before an initial read or write operation after
power up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If OE is
HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Document Number: 38-06016 Rev. *H
Page 4 of 22
CY7C4221 / CY7C4231
Architecture
The CY7C42X1 consists of an array of 1K or 2K words of nine
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK,
REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF).
Write Enable 2/Load (WEN2/LD).
This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags or
to have two write enables, which allows depth expansion. If Write
Enable 2/Load (WEN2/LD) is set active HIGH at Reset
(RS = LOW), this pin operates as a second write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2 / Load (WEN2/LD)
is HIGH, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every Write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
Resetting the FIFO
During powerup, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q
0–8
) go LOW t
RSF
after the
rising edge of RS. For the FIFO to reset to its default state, a
falling edge must occur on RS and the user must not read or write
while RS is LOW. All flags are guaranteed to be valid t
RSF
after
RS is taken LOW.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1 for writing or reading data to these
registers.
When the device is configured for programmable flags and both
WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition
of WCLK writes data from the data inputs to the empty offset least
significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and
full offset MSB register, respectively, when WEN2/LD and WEN1
are LOW. The fifth LOW-to-HIGH transition of WCLK while
WEN2/LD and WEN1 are LOW writes data to the empty LSB
register again.
Figure 2 on page 6
shows the registers sizes and
default values for the various device types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read
and write operation. The next time WEN2/LD is brought LOW, a
write operation stores data in the next offset register in
sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK Read register contents
to the data outputs. Writes and reads should not be preformed
simultaneously on the offset registers.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D
0–8
pins is written into the FIFO on each
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory is
presented on the Q
0–8
outputs. New data is presented on each
rising edge of RCLK while REN1 and REN2 are active. REN1
and REN2 must set up t
ENS
before RCLK for it to be a valid read
function. WEN1 and WEN2 must occur t
ENS
before WCLK for it
to be a valid write function.
An output enable (OE) pin is provided to three-state the Q
0–8
outputs when OE is asserted. When OE is enabled (LOW), data
in the output register is available to the Q
0–8
outputs after t
OE
.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
0–8
outputs even
after additional reads occur.
Write Enable 1 (WEN1).
If the FIFO is configured for
programmable flags, Write Enable 1 (WEN1) is the only write
enable control pin. In this configuration, when Write Enable 1
(WEN1) is LOW, data can be loaded into the input register and
RAM array on the LOW-to-HIGH transition of every Write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
Document Number: 38-06016 Rev. *H
Page 5 of 22
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