CY7C1371D
CY7C1373D
18-Mbit (512 K × 36/1 M × 18) Flow-Through
SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture
Features
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Functional Description
The CY7C1371D/CY7C1373D is a 3.3 V, 512 K × 36/1 M × 18
synchronous flow through burst SRAM designed specifically to
support unlimited true back-to-back read/write operations with
no wait state insertion. The CY7C1371D/CY7C1373D is
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four byte write
select (BW
X
) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
No Bus Latency (NoBL) architecture eliminates dead cycles
between write and read cycles
Supports up to 133-MHz bus operations with zero wait states
❐
Data is transferred on every clock
Pin-compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte write capability
3.3 V/2.5 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
6.5 ns (for 133-MHz device)
Clock enable (CEN) pin to enable clock and suspend operation
Synchronous self-timed writes
Asynchronous output enable
Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 119-ball BGA, and 165-ball FBGA packages
Three chip enables for simple depth expansion
Automatic power-down feature available using ZZ mode or CE
deselect
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability – linear or interleaved burst order
Low standby power
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Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
133 MHz
6.5
210
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 38-05556 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 5, 2012
CY7C1371D
CY7C1373D
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 9
Functional Overview ...................................................... 10
Single Read Accesses .............................................. 10
Burst Read Accesses ................................................ 10
Single Write Accesses ............................................... 10
Burst Write Accesses ................................................ 11
Sleep Mode ............................................................... 11
Interleaved Burst Address Table ............................... 11
Linear Burst Address Table ....................................... 11
ZZ Mode Electrical Characteristics ............................ 11
Truth Table ...................................................................... 12
Partial Truth Table for Read/Write ................................ 12
Partial Truth Table for Read/Write ................................ 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
Test Access Port (TAP) ............................................. 14
PERFORMING A TAP RESET .................................. 14
TAP REGISTERS ...................................................... 14
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 16
TAP Controller Block Diagram ...................................... 17
TAP Timing ...................................................................... 17
TAP AC Switching Characteristics ............................... 18
3.3 V TAP AC Test Conditions ....................................... 19
3.3 V TAP AC Output Load Equivalent ......................... 19
2.5 V TAP AC Test Conditions ....................................... 19
2.5 V TAP AC Output Load Equivalent ......................... 19
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 19
Identification Register Definitions ................................ 20
Scan Register Sizes ....................................................... 20
Identification Codes ....................................................... 20
Boundary Scan Order .................................................... 21
Boundary Scan Order .................................................... 22
Maximum Ratings ........................................................... 23
Operating Range ............................................................. 23
Electrical Characteristics ............................................... 23
Capacitance .................................................................... 24
Thermal Resistance ........................................................ 24
AC Test Loads and Waveforms ..................................... 25
Switching Characteristics .............................................. 26
Switching Waveforms .................................................... 27
Ordering Information ...................................................... 30
Ordering Code Definitions ......................................... 30
Package Diagrams .......................................................... 31
Acronyms ........................................................................ 34
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
Document History Page ................................................. 35
Sales, Solutions, and Legal Information ...................... 37
Worldwide Sales and Design Support ....................... 37
Products .................................................................... 37
PSoC Solutions ......................................................... 37
Document Number: 38-05556 Rev. *L
Page 4 of 37
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