CY7C1351G
4-Mbit (128 K × 36) Flow-Through SRAM
with NoBL™ Architecture
4-Mbit (128 K × 36) Flow-Through SRAM with NoBL™ Architecture
Features
■
Functional Description
The CY7C1351G is a 3.3 V, 128 K × 36 synchronous
flow-through burst SRAM designed specifically to support
unlimited true back-to-back read/write operations without the
insertion of wait states. The CY7C1351G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to enable
consecutive Read/Write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the four byte write select
(BW
[A:D]
) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
Can support up to 133-MHz bus operations with zero wait
states
❐
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need
to use OE
Registered inputs for flow-through operation
Byte write capability
128 K × 36 common I/O architecture
2.5 V/3.3 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
6.5 ns (for 133-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
Burst capability – linear or interleaved burst order
Low standby power
■
■
■
■
■
■
■
■
■
■
■
■
■
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
133 MHz
6.5
225
40
100 MHz
8.0
205
40
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 38-05513 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 5, 2012
CY7C1351G
Logic Block Diagram
A0, A1, A
MODE
CLK
CEN
C
CE
ADV/LD
C
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
A1
D1
A0
D0
Q1 A1'
A0'
Q0
BURST
LOGIC
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
DQP
C
DQP
D
OE
CE1
CE2
CE3
ZZ
INPUT
E
REGISTER
READ LOGIC
SLEEP
Control
Document Number: 38-05513 Rev. *K
Page 2 of 20
CY7C1351G
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Burst Read Accesses .................................................. 6
Single Write Accesses ................................................. 6
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 7
Linear Burst Address Table ......................................... 7
Interleaved Burst Address Table ................................. 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Partial Truth Table for Read/Write .................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC Solutions ......................................................... 20
Document Number: 38-05513 Rev. *K
Page 3 of 20
CY7C1351G
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
ADV/LD
NC/18M
BW
D
BW
C
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
CEN
CLK
WE
OE
A
A
NC/9M
A
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
BYTE C
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
BYTE D
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
81
A
CY7C1351G
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44
45
46
47
48
49
50
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
39
40
41
42
NC/72M
NC/288M
NC/144M
MODE
NC/36M
A1
A0
V
SS
V
DD
A
A
A
A
43
A
A
A
Document Number: 38-05513 Rev. *K
A
A
A
A
Page 4 of 20
CY7C1351G
Pin Definitions
Name
A
0
, A
1
, A
BW
[A:D]
WE
ADV/LD
I/O
Description
Input-
Address inputs used to select one of the 128 K address locations.
Sampled at the rising edge of
synchronous the CLK. A
[1:0]
are fed to the two-bit burst counter.
Input-
Byte write inputs, active LOW.
Qualified with WE to conduct writes to the SRAM. Sampled on the rising
synchronous edge of CLK.
Input-
Write enable input, active LOW.
Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
Input-
Advance/load input.
Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to
load a new address.
Input-clock
Clock input.
Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CLK
CE
1
CE
2
CE
3
OE
Input-
Chip enable 1 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
,
synchronous and CE
3
to select/deselect the device.
Input-
Chip enable 2 input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
3
to select/deselect the device.
Input-
Chip enable 3 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
2
to select/deselect the device.
Input-
Output enable, asynchronous input, active LOW.
Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Input-
Clock enable input, active LOW.
When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
Input-
ZZ “sleep” input.
This active HIGH input places the device in a non-time critical “sleep” condition with data
asynchronous integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an internal
pull-down.
I/O-
Bidirectional data I/O lines.
As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ
s
and
DQP
[A:D]
are placed in a tristate condition. The outputs are automatically tristated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
I/O-
Bidirectional data parity I/O lines.
Functionally, these signals are identical to DQ
s
. During write
synchronous sequences, DQP
[A:D]
is controlled by BW
[A:D]
correspondingly.
Input
strap pin
I/O power
supply
Ground
–
Mode input. Selects the burst order of the device.
When tied to GND selects linear burst sequence.
When tied to V
DD
or left floating selects interleaved burst sequence.
Power supply for the I/O circuitry.
Ground for the device.
No connects.
Not Internally connected to the die.
CEN
ZZ
DQ
s
DQP
[A:D]
MODE
V
DD
V
DDQ
V
SS
NC
Power supply
Power supply inputs to the core of the device.
Document Number: 38-05513 Rev. *K
Page 5 of 20
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
