CY7C1350G
4-Mbit (128 K × 36) Pipelined SRAM
with NoBL™ Architecture
4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture
Features
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Functional Description
The CY7C1350G is a 3.3 V, 128 K × 36 synchronous-pipelined
burst SRAM designed specifically to support unlimited true
back-to-back read/write operations without the insertion of wait
states. The CY7C1350G is equipped with the advanced No Bus
Latency™ (NoBL™) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of the
SRAM, especially in systems that require frequent write/read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which, when
deasserted, suspends operation and extends the previous clock
cycle. Maximum access delay from the clock rise is 2.8 ns
(200-MHz device).
Write operations are controlled by the four byte write select
(BW
[A:D]
) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
Pin compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need
to use OE
Byte write capability
128 K × 36 common I/O architecture
3.3 V power supply (V
DD
)
2.5 V / 3.3 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
2.8 ns (for 200-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable (OE)
Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option
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Logic Block Diagram
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
DQP
C
DQP
D
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Cypress Semiconductor Corporation
Document Number: 38-05524 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 24, 2012
CY7C1350G
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Burst Read Accesses .................................................. 6
Single Write Accesses ................................................. 6
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Partial Truth Table for Read/Write .................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC Solutions ......................................................... 21
Document Number: 38-05524 Rev. *L
Page 2 of 21
CY7C1350G
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
200 MHz
2.8
265
40
133 MHz
4.0
225
40
Unit
ns
mA
mA
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
ADV/LD
NC/18M
NC/9M
BW
D
BW
C
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
CEN
CLK
WE
OE
A
A
A
82
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
BYTE C
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
BYTE D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
81
80
79
78
77
76
75
74
73
72
71
70
69
A
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE A
BYTE B
CY7C1350G
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
A
49
A
MODE
V
DD
V
SS
A
1
A
0
NC/288M
NC/144M
NC/72M
NC/36M
A
A
A
A
A
A
A
A
Document Number: 38-05524 Rev. *L
A
50
Page 3 of 21
CY7C1350G
Pin Configurations
(continued)
Figure 2. 119-Ball BGA (14 × 22 × 2.4 mm) pinout
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC/144M
NC
V
DDQ
2
A
CE
2
A
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
A
NC/72M
NC
3
A
A
A
V
SS
V
SS
V
SS
BW
C
V
SS
V
SS
V
SS
BW
D
V
SS
V
SS
V
SS
MODE
A
NC
4
NC/18M
ADV/LD
V
DD
NC
CE
1
OE
NC/9M
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
A
NC
5
A
A
A
V
SS
V
SS
V
SS
BW
B
V
SS
V
SS
V
SS
BW
A
V
SS
V
SS
V
SS
NC
A
NC
6
A
CE
3
A
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
NC/36M
NC
7
V
DDQ
NC
NC
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC/288M
ZZ
V
DDQ
Document Number: 38-05524 Rev. *L
Page 4 of 21
CY7C1350G
Pin Definitions
Name
A
0
, A
1
, A
BW
[A:D]
WE
ADV/LD
I/O
Description
Input-
Address inputs used to select one of the 128 K address locations.
Sampled at the rising edge of
synchronous the CLK. A
[1:0]
are fed to the two-bit burst counter.
Input-
Byte write inputs, active LOW.
Qualified with WE to conduct writes to the SRAM. Sampled on the rising
synchronous edge of CLK.
Input-
Write enable input, active LOW.
Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
Input-
Advance/load input.
Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to
load a new address.
Input-clock
Clock input.
Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CLK
CE
1
CE
2
CE
3
OE
Input-
Chip enable 1 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
synchronous and CE
3
to select/deselect the device.
Input-
Chip enable 2 input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
3
to select/deselect the device.
Input-
Chip enable 3 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
2
to select/deselect the device.
Input-
Output enable, asynchronous input, active LOW.
Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Input-
Clock enable input, active LOW.
When asserted LOW the Clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
Input-
ZZ “sleep” input.
This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an
internal pull-down.
I/O-
Bidirectional data I/O lines.
As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ
s
and
DQP
X
are placed in a tristate condition. The outputs are automatically tri-stated during the data portion of
a write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
I/O-
Bidirectional data parity I/O lines.
Functionally, these signals are identical to DQ
s
. During write
synchronous sequences, DQP
[A:D]
is controlled by BW
[A:D]
correspondingly.
Input
strap pin
I/O power
supply
Ground
–
Mode input. Selects the burst order of the device.
When tied to GND selects linear burst sequence.
When tied to V
DD
or left floating selects interleaved burst sequence.
Power supply for the I/O circuitry.
Ground for the device.
No Connects.
Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are address
expansion pins in this device and will be used as address pins in their respective densities.
CEN
ZZ
DQs
DQP
[A:D]
MODE
V
DD
V
DDQ
V
SS
NC
Power supply
Power supply inputs to the core of the device.
Document Number: 38-05524 Rev. *L
Page 5 of 21
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