CY7C1328G
4-Mbit (256 K × 18)
Pipelined DCD Sync SRAM
4-Mbit (256 K × 18) Pipelined DCD Sync SRAM
Features
■
■
Functional Description
The CY7C1328G SRAM integrates 256 K × 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE
1
), depth-expansion
chip enables (CE
2
and CE
3
), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW
[A:B]
, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see
Pin Definitions on page 5
and
Truth Table on
page 8
for further details). Write cycles can be one to two bytes
wide as controlled by the byte write control inputs. GW active
LOW causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off the
output buffers an additional cycle when a deselect is executed.
This feature allows depth expansion without penalizing system
performance.
The CY7C1328G operates from a +3.3 V core power supply
while all outputs operate with a +3.3 V or a +2.5 V supply. All
inputs and outputs are JEDEC-standard JESD8-5-compatible.
Registered inputs and outputs for pipelined operation
Optimal for performance (double-cycle deselect)
❐
Depth expansion without wait state
256 K × 18 common I/O architecture
3.3 V core power supply (V
DD
)
3.3 V/2.5 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
4.0 ns (for 133-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
“ZZ” sleep mode option
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Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
133 MHz
4.0
225
40
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 38-05523 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 25, 2012
CY7C1328G
Functional Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
ENABLE
REGISTER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A,
DQP
A
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BW
B
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQ
s,
DQP
A
DQP
B
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document Number: 38-05523 Rev. *J
Page 2 of 22
CY7C1328G
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagram ............................................................ 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Document Number: 38-05523 Rev. *J
Page 3 of 22
CY7C1328G
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
BYTE B
V
DDQ
V
SSQ
NC
NC
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQP
B
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
A
CE
1
CE
2
NC
NC
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
CY7C1328G
A
NC
NC
V
DDQ
V
SSQ
NC
DQP
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
BYTE A
MODE
A
A
A
A
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
Document Number: 38-05523 Rev. *J
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 4 of 22
CY7C1328G
Pin Definitions
Pin
A
0
, A
1
, A
TQFP
Type
Description
Input-
Address inputs used to select one of the 256 K address locations.
Sampled at the
37, 36, 32, 33,
34, 35, 44, 45, synchronous rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are
46, 47, 48, 49,
sampled active. A
[1:0]
are fed to the two-bit counter.
50, 80, 81, 82,
99, 100
93,94
88
Input-
Byte write select inputs, active LOW.
Qualified with BWE to conduct byte writes to the
synchronous SRAM. Sampled on the rising edge of CLK.
Input-
Global write enable input, active LOW.
When asserted LOW on the rising edge of CLK,
synchronous a global write is conducted (all bytes are written, regardless of the values on BW
[A:B]
and
BWE).
Input-
Byte write enable input, active LOW.
Sampled on the rising edge of CLK. This signal
synchronous must be asserted LOW to conduct a byte write.
Input-
clock
Clock input.
Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
BW
A
, BW
B
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
87
89
98
Input-
Chip enable 1 input, active LOW.
Sampled on the rising edge of CLK. Used in
synchronous conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is
HIGH. CE
1
is sampled only when a new external address is loaded.
Input-
Chip enable 2 input, active HIGH.
Sampled on the rising edge of CLK. Used in
synchronous conjunction with CE
1
and CE
3
to select/deselect the device. CE
2
is sampled only when
a new external address is loaded.
Input-
Chip enable 3 input, active LOW.
Sampled on the rising edge of CLK. Used in
synchronous conjunction with CE
1
and CE
2
to select/deselect the device. CE
3
is sampled only when
a new external address is loaded.
Input-
Output enable, asynchronous input, active LOW.
Controls the direction of the I/O pins.
asynchronous When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
Advance input signal, sampled on the rising edge of CLK, active LOW.
When
asserted, it automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Input-
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
synchronous When asserted LOW, addresses presented to the device are captured in the address
registers. A
[1:0]
are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
Input-
ZZ “sleep” input, active HIGH.
When asserted HIGH places the device in a
asynchronous non-time-critical “sleep” condition with data integrity preserved. During normal operation,
this pin has to be low or left floating. ZZ pin has an internal pull-down.
Input-
synchronous
Input-
synchronous
97
92
86
ADV
ADSP
83
84
ADSC
85
ZZ
64
DQs,
DQP
[A:B]
58, 59, 62, 63,
I/O-
Bidirectional data I/O lines.
As inputs, they feed into an on-chip data register that is
68, 69, 72, 73, synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
74, 8, 9, 12,
memory location specified by the addresses presented during the previous clock rise of
13, 18, 19, 22,
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
23, 24
the pins behave as outputs. When HIGH, DQs and DQP
[A:B]
are placed in a tristate
condition.
15, 41, 65, 91 Power supply
Power supply inputs to the core of the device.
17, 40, 67, 90
Ground
Ground for the core of the device.
4, 11, 20, 27,
I/O power
Power supply for the I/O circuitry.
54, 61, 70, 77
supply
5, 10, 21, 26,
55, 60, 71, 76
I/O ground
Ground for the I/O circuitry.
V
DD
V
SS
V
DDQ
V
SSQ
Document Number: 38-05523 Rev. *J
Page 5 of 22
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