January 2001
Si4822DY
Single N-Channel, Logic Level, PowerTrench
®
MOSFET
GeneralDescription
This N-Channel Logic Level MOSFET is produced
using Fairchild Semiconductor's advanced PowerTrench
process that has been especially tailored to minimize
the on-state resistance and yet maintain superior
switching performance.
These devices are well suited for low voltage and battery
powered applications where low in-line power loss and
fast switching are required.
Features
12.5 A, 30 V. R
DS(ON)
= 0.0095
Ω
@ V
GS
= 10 V
R
DS(ON)
= 0.013
Ω
@ V
GS
= 4.5 V.
Fast switching speed.
Low gate charge.
High performance trench technology for
extremely low R
DS(ON)
.
High power and current handling capability.
SOT-23
SuperSOT
TM
-6
SuperSOT
TM
-8
SO-8
SOT-223
SOIC-16
D
D
D
D
5
4
3
2
1
2
48
2
G
6
7
SO-8
pin
1
S
S
S
8
Absolute Maximum Ratings
Symbol
Parameter
T
A
= 25
o
C unless other wise noted
Si4822DY
Units
V
DSS
V
GSS
I
D
P
D
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
(Note 1a)
30
±20
12.5
50
2.5
1.2
1
-55 to 150
V
V
A
W
T
J
,T
STG
R
θ
JA
R
θ
JC
Operating and Storage Temperature Range
°C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
50
25
°C/W
°C/W
© 2001 Fairchild Semiconductor International
Si4822DY Rev.A
Electrical Characteristics
(
T
A
= 25
O
C unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
V
GS
= 0 V, I
D
= 250 µA
I
D
= 250 µA, Referenced to 25
o
C
V
DS
= 24 V, V
GS
= 0 V
T
J
= 55°C
V
GS
= 20 V, V
DS
= 0 V
V
GS
= -20 V, V
DS
= 0 V
I
D
= 250 µA, Referenced to 25
o
C
V
DS
= V
GS
, I
D
= 250 µA
T
J
=125°C
V
GS
= 10 V, I
D
= 12.5 A
T
J
=125°C
V
GS
= 4.5 V, I
D
= 10.5 A
30
33
1
10
100
-100
V
mV /
o
C
µA
µA
nA
nA
mV /
o
C
3
2.4
0.0095
0.016
0.013
A
35
2180
500
255
S
pF
pF
pF
24
26
70
27
33
ns
ns
ns
ns
nC
nC
nC
2.1
A
V
V
∆
BV
DSS
/
∆
T
J
I
DSS
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
(Note 2)
ON CHARACTERISTICS
∆
V
GS(th)
/
∆
T
J
V
GS(th)
R
DS(ON)
Gate Threshold Voltage Temp. Coefficient
Gate Threshold Voltage
-4.5
1
0.8
1.6
1.3
0.008
0.012
0.0105
25
Static Drain-Source On-Resistance
Ω
I
D(ON)
g
FS
C
iss
C
oss
C
rss
t
D(on)
t
r
t
D(off)
t
f
Q
g
Q
gs
Q
gd
I
S
V
SD
Notes:
On-State Drain Current
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(Note 2)
V
GS
= 10 V, V
DS
= 5 V
V
DS
= 15 V, I
D
= 12.5 A
V
DS
= 15 V, V
GS
= 0 V,
f = 1.0 MHz
DYNAMIC CHARACTERISTICS
SWITCHING CHARACTERISTICS
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V
DS
= 10 V, I
D
= 1 A
V
GS
= 10 V , R
GEN
=
6 Ω
13
14
43
15
V
DS
= 15 V, I
D
= 12.5 A,
V
GS
= 5 V
23
7
11
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 2.1 A
(Note 2)
0.72
1.2
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is
guaranteed by design while R
θ
CA
is determined by the user's board design.
a. 50
O
C/W on a 1 in
2
pad
of 2oz copper.
b. 105
O
C/W on a 0.04 in
2
pad of 2oz copper.
c. 125
O
C/W on a 0.006 in
2
pad
of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Si4822DY Rev.A
Typical Electrical Characteristics
50
I
D
, DRAIN-SOURCE CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 10V
6.0V
3
R
DS(ON)
, NORMALIZED
40
4.5V
4.0V
3.5V
2.5
V
GS
= 3.0V
30
2
20
3.0V
3.5 V
4.0 V
4.5 V
5.5V
7.0V
10V
50
1.5
10
2.5V
0
0
0.5
1
1.5
2
V
DS
, DRAIN-SOURCE VOLTAGE (V)
1
0
10
20
30
40
I
D
, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.8
DRAIN-SOURCE ON-RESISTANCE
I
D
= 12.5A
R
DS(ON)
, ON-RESISTANCE (OHM)
0.04
I
D
= 6.3A
1.6
1.4
1.2
1
0.8
0.6
-50
V
GS
= 10V
R
DS(ON)
, NORMALIZED
0.03
0.02
125°C
0.01
25°C
0
-25
0
25
50
75
100
125
150
2
4
6
8
10
T , JUNCTION TEMPERATURE (°C)
J
V
GS
, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation
Temperature.
with
Figure 4 . On Resistance Variation with
Gate-to-Source Voltage.
50
40
TJ = -55°C
I
S
, REVERSE DRAIN CURRENT (A)
V
DS
=5.0V
I
D
, DRAIN CURRENT (A)
40
25°C
125°C
10
1
0.1
0.01
0.001
0.0001
0
V
GS
= 0V
TJ = 125°C
25°C
-55°C
30
20
10
0
1
2
3
4
V
GS
, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 5 . Transfer Characteristics.
Figure 6 . Body Diode Forward Voltage
Variation with Source Current
and Temperature.
Si4822DY Rev.A
Typical Electrical And Thermal Characteristics
10
V
GS
, GATE-SOURCE VOLTAGE (V)
4000
I
D
= 12.5A
8
V
DS
= 5V
10V
CAPACITANCE (pF)
2000
Ciss
15V
6
1000
Coss
400
4
C
rss
200
2
f = 1 MHz
V
GS
= 0 V
0.2
0.5
1
2
5
10
30
0
0
10
20
30
40
50
60
Q
g
, GATE CHARGE (nC)
100
0.1
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
100
30
I
D
, DRAIN CURRENT (A)
10
3
1
S
RD
(O
N)
LIM
IT
50
0.1
V
GS
=10V
SINGLE PULSE
R
θ
JA
= 125°C/W
A
T
A
= 25°C
0.1
0.5
1
2
100
us
1m
s
10m
s
100
ms
1s
10s
DC
40
POWER (W)
SINGLE PULSE
R
θ
JA
=125°C/W
T
A
= 25°C
30
20
10
0.01
0.05
5
10
30
50
0
0.001
0.01
0.1
1
10
100 300
SINGLE PULSE TIME (SEC)
V
DS
, DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
0.5
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
0.0001
0.001
0.01
0.1
t
1
, TIME (sec)
1
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
P(pk)
R
θ
JA
(t) = r(t) * R
θ
JA
R
θ
JA
= 125°C/W
t
1
t
2
T
J
- T
A
= P * R
θ
JA(t)
Duty Cycle, D = t
1
/t
2
10
100
300
Figure 11. Transient Thermal Response Curve .
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
Si4822DY Rev.A
SOIC-8 Tape and Reel Data
SOIC(8lds) Packaging
Configuration:
Figure 1.0
Packaging Description:
EL ECT ROST AT IC
SEN SIT IVE DEVICES
DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC
EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S
TNR D ATE
PT NUMB ER
PEEL STREN GTH MIN ___ __ ____ __ ___gms
MAX ___ ___ ___ ___ _ gms
Antistatic Cover Tape
ESD Label
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
Static Dissipative
Embossed Carrier Tape
F63TNR
Label
Customized
Label
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
SOIC (8lds) Packaging Information
Pin 1
D84Z
TNR
500
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Standard
(no flow code)
TNR
2,500
L86Z
Rail/Tube
95
F011
TNR
4,000
SOIC-8 Unit Orientation
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight per Reel (kg)
13" Dia
343x64x343
5,000
0.0774
0.6060
-
530x130x83
30,000
0.0774
-
13" Dia
343x64x343
8,000
0.0774
0.9696
7" Dia
184x187x47
1,000
0.0774
0.1182
Note/Comments
343mm x 342mm x 64mm
Standard Intermediate box
ESD Label
F63TNR Label sample
LOT: CBVK741B019
FSID: FDS9953A
QTY: 2500
SPEC:
F63TNLabel
F63TN Label
ESD Label
(F63TNR)3
D/C1: D9842
D/C2:
QTY1:
QTY2:
SPEC REV:
CPN:
N/F: F
SOIC(8lds) Tape Leader and Trailer
Configuration:
Figure 2.0
Carrier Tape
Cover Tape
Components
Trailer Tape
640mm minimum or
80 empty pockets
Leader Tape
1680mm minimum or
210 empty pockets
©2000 Fairchild Semiconductor International
July 1999, Rev. B
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