Caution in Setting the UART Noise Rejection Time
When UART is used, settings of RXDNC are limited depending on the transfer clock specified by BRG. The com-
bination "O" is available but please do not select the combination "–".
The transfer clock generated by timer/counter interrupt is calculated by the following equation :
Transfer clock [Hz] = Timer/counter source clock [Hz]
÷
TTREG set value
RXDNC setting
BRG setting
Transfer
clock [Hz]
01
(Reject pulses shorter
than 31/fc[s] as noise)
O
–
O
O
O
10
(Reject pulses shorter
than 63/fc[s] as noise)
O
–
–
O
O
11
(Reject pulses shorter
than 127/fc[s] as
noise)
–
–
–
–
O
00
(No noise rejection)
000
110
(When the transfer clock gen-
erated by timer/counter inter-
rupt is the same as the right
side column)
fc/13
fc/8
fc/16
fc/32
O
O
O
O
O
The setting except the above
2008-09-30
TMP87CH48/CM48
Important Notices
Thank you for your continued patronage of Toshiba microcontrollers.
This page gives you important information on using Toshiba microcontrollers. Please be sure to check each
item for proper use of our products.
2008-02-08
TMP87CH48/CM48
TOSHIBA Microcontrollers
870 Family
(TMP87CH48U) (TMP87CH48DF) (TMP87CM48U) (TMP87CM48DF)
（TMP87CH48I）
(TMP87PH48U) (TMP87PH48DF) (TMP87PM48U) (TMP87PM48DF)
Datasheet Modifications: I
2
C Bus Mode Control
The following problem is included in the explanation of the I
2
C bus function of this data sheet.
It will guide the correction as follows. Please read it for the explanation of this data sheet as follows.
Section: “I
2
C Bus Mode Control”
▪
In the explanation of the Serial Bus Interface Control Register 1
1. Delete the setting examples where the serial clock frequency exceeds 100 kHz.
2. Add the following note.
000 :
Reserved
001 :
Reserved
010 : 58.8
SCK
Serial clock selection
011 : 30.3
100 : 15.4
101 : 7.75
110 : 3.89
111 : reserved
Note: This I C bus circuit does not support the Fast mode. It supports the Standard mode only. Although
the I C bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the I C
specification is not guaranteed in that case.
2
2
2
(Note)
(Note)
kHz
kHz
kHz
kHz
kHz
at fc = 8MHz (Output on SCL
pin)
Write-
only
▪
In “(3) Serial clock”
1. Add the following sentence about the communication baud rate.
a. Clock source
The SCK (bits 2 to 0 in the SBICR1) is used to select a maximum transfer frequency
outputed on the SCL pin in the master mode.
Set a communication baud rate that meets
the I
2
C bus specification, such as the shortest pulse width of t
LOW,
based on the equations
shown below.
In both master mode and slave mode, a pulse width of at least 4 machine cycles is require
for both “H” and “L” levels.
t
LOW
= 2 /f
c
t
HIGH
= 2 /f
c
+
8/f
c
fscl = 1/(t
Low
+
t
HIGH
)
n
n
2008-02-08
微控制器 MCU
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