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UM10601
LPC800 User manual
Rev. 1.0 — 7 November 2012
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Preliminary user manual
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Document information
Info
Keywords
Content
ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8,
LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20,
LPC812M101FDH20
LPC800 Preliminary user manual
Abstract
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NXP Semiconductors
UM10601
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LPC800 User manual
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Revision history
Rev
1
Date
20121107
Description
Preliminary LPC800 user manual
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Contact information
For more information, please visit:
http://www.nxp.com
For sales office addresses, please send an email to:
salesaddresses@nxp.com
UM10601
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Preliminary user manual
Rev. 1.0 — 7 November 2012
2 of 313
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UM10601
Rev. 1.0 — 7 November 2012
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Chapter 1: LPC800 Introductory information
Preliminary user manual
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1.1 Introduction
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The LPC800 are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The UM10601 support up to 16 kB of flash memory
and 4 kB of SRAM.
The peripheral complement of the UM10601 includes a CRC engine, one I
2
C-bus
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up
timer, and state-configurable timer, one comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O
pins.
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1.2 Features
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System:
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ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz.
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ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
–
Micro Trace Buffer
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System tick timer
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Memory:
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16 kB on-chip flash programming memory.
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4 kB SRAM.
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In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot loader software.
•
Boot ROM API support:
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UART drivers
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I2C drivers
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Power profiles
–
IAP/ISP
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Digital peripherals:
–
High-speed GPIO interface connected to the ARM Cortex-M0+ I/O port with up to
18 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
–
Pin interrupt generation capability with boolean pattern-matching feature onup to
eightselectable GPIO inputs.
–
Switch matrix for flexible configuration of each I/O pin function.
–
State Configurable Timer (SCT) with input and output functions (including capture
and match) assigned to pins through the switch matrix.
–
Multiple-channel multi-rate timer for repetitive interrupt generation at up to four
programmable, fixed rates.
–
Wake-up timer for self-timed wake-up from reduced power modes.
UM10601
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Preliminary user manual
Rev. 1.0 — 7 November 2012
3 of 313
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NXP Semiconductors
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Chapter 1: LPC800 Introductory information
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CRC engine.
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Windowed Watchdog timer
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Analog peripherals:
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Comparator with external voltage reference with pin functions assigned through
the switch matrix.
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Internal reference voltage.
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•
Serial interfaces:
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Three UART interfaces with pin functions assigned through the switch matrix.
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Two SPI controllers with pin functions assigned through the switch matrix.
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One I
2
C-bus interface with open-drain full I2C spec fast Modeplus.
•
Clock generation:
–
12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
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Crystal oscillator with an operating range of 1 MHz to 25 MHz.
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Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
–
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the external clock input (CLKIN), the
system oscillator, or the internal RC oscillator.
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Power control:
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Integrated PMU (Power Management Unit) to minimize power consumption.
–
Reduced power modes (Sleep, deep-sleep, power-down, deep power-down).
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Power-On Reset (POR).
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Brownout detect.
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Unique device serial number for identification.
•
Single power supply.
•
Available in a SO20 package, TSSOP20 package, TSSOP16, and DIP8 package.
UM10601
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Preliminary user manual
Rev. 1.0 — 7 November 2012
4 of 313
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NXP Semiconductors
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Chapter 1: LPC800 Introductory information
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1.3 Ordering information
Table 1.
Ordering information
Package
Name
LPC810M021FN8
LPC811M001FDH16
LPC812M101FDH16
LPC812M101FD20
LPC812M101FDH20
Table 2.
DIP8
TSSOP16
TSSOP16
SO20
TSSOP20
Description
plastic dual in-line package; 8 leads (300 mil)
Type number
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Version
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SOT097-2
SOT403-1
SOT403-1
SOT163-1
SOT360-1
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
plastic small outline package; 20 leads; body width 7.5 mm
plastic thin shrink small outline package; 20 leads; body width 4.4 mm
Ordering options
Flash/kB SRAM/kB USART
4
8
16
16
16
1
2
4
4
4
2
2
3
2
3
I
2
C
1
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1
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SPI
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2
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Comparator
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GPIO
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14
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18
18
Package
DIP8
TSSOP16
TSSOP16
SO20
TSSOP20
Type number
LPC810M021FN8
LPC811M001FDH16
LPC812M101FDH16
LPC812M101FD20
LPC812M101FDH20
UM10601
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Preliminary user manual
Rev. 1.0 — 7 November 2012
5 of 313
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