THC63LVD103D _Rev.3.0_E
THC63LVD103D
160MHz 30Bits COLOR LVDS Transmitter
General Description
The THC63LVD103D transmitter is designed to sup-
port pixel data transmission between Host and Flat
Panel Display from NTSC up to 1080p(60Hz).
The THC63LVD103D converts 35bits of CMOS/TTL
data into LVDS(Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for ris-
ing edge or falling edge clocks through a dedicated pin.
At a transmit clock frequency of 160MHz, 30bits of
RGB data and 5bits of timing and control data
(HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmit-
ted at an effective rate of 1.12Gbps per LVDS channel.
Features
•
Wide dot clock range: 8-160MHz suited for NTSC,
VGA, SVGA, XGA,SXGA and SXGA+ and 1080p
•
•
•
•
•
•
•
•
•
PLL requires no external components
Supports spread spectrum clock generator
On chip jitter filtering
Clock edge selectable
Supports reduced swing LVDS for low EMI
Power down mode
Low power single 3.3V CMOS design
64pin TQFP
Pin compatible with THC63LVD103(30bits)
Block Diagram
CMOS/TTL INPUT
TA0-6
TB0-6
TC0-6
7
7
7
PARALLEL TO SERIAL
LVDS OUTPUT
TA +/-
TB +/-
TC +/-
TD0-6
TE0-6
7
TD +/-
7
TE +/-
CLK IN
(8 to160MHz)
RS
R/F
/PDWN
PLL
TCLK +/-
(8 to 160MHz)
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.
THC63LVD103D _Rev.3.0_E
Pin Out
TB6
TC0
VCC
TC1
TC2
TC3
TC4
GND
TC5
TC6
TD0
R/F
TD1
TD2
TD3
TD4
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TB5
GND
TB4
TB3
TB2
RS
TB1
TB0
TA6
GND
TA5
TA4
TA3
TA2
TA1
TA0
LVDS GND
TA-
TA+
TB-
TB+
LVDS VCC
LVDS GND
TC-
TC+
TCLK-
TCLK+
TD-
TD+
TE-
TE+
LVDS GND
Copyright©2011 THine Electronics, Inc.
TD5
GND
TD6
TE0
TE1
TE2
VCC
TE3
TE4
GND
TE5
CL K I N
/PDWN
PL L GND
PL L VCC
TE6
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THine Electronics, Inc.
THC63LVD103D _Rev.3.0_E
Pin Description
Pin Name
TA+, TA-
TB+, TB-
TC+, TC-
TD+, TD-
TE+,TE-
TCLK+,
TCLK-
TA0 ~ TA6
TB0 ~ TB6
TC0 ~ TC6
TD0 ~ TD6
TE0 ~ TE6
/PDWN
Pin #
30, 31
28, 29
24, 25
20, 21
18, 19
22, 23
33,34,35,36,37,38,40
41,42,44,45,46,48,49
50,52,53,54,55,57,58
59,61,62,63,64,1,3
4,5,6,8,9,11,16
13
Type
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
LVDS OUT
IN
IN
IN
IN
IN
IN
H: Normal operation,
L: Power down (all outputs are Hi-Z)
LVDS swing mode, VREF select.See Fig4, 5.
Pixel Data Inputs.
LVDS Clock Out.
LVDS Data Out.
Description
RS
LVDS
Swing
350mV
350mV
200mV
Small Swing
Input Support
N/A
RS=VREF
a
N/A
RS
43
IN
VCC
0.6 ~ 1.4V
GND
a. VREF is Input Reference Voltage.
R/F
VCC
CLKIN
GND
LVDS VCC
LVDS GND
PLL VCC
PLL GND
60
51, 7
12
2, 10, 39, 47, 56
27
17, 26, 32
15
14
IN
Power
IN
Ground
Power
Ground
Power
Ground
Input Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
Power Supply Pins for TTL inputs and digital
circuitry.
Clock in.
Ground Pins for TTL inputs and digital circuitry.
Power Supply Pins for LVDS Outputs.
Ground Pins for LVDS Outputs.
Power Supply Pin for PLL circuitry.
Ground Pins for PLL circuitry.
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.
THC63LVD103D _Rev.3.0_E
Absolute Maximum Ratings
1
Supply Voltage (V
CC
)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Transmitter Output Voltage
Junction Temperature
Storage Temperature Range
Reflow Peak Temperature / Time
Maximum Power Dissipation @+25
°C
-0.3V ~ +4.0V
-0.3V ~ (V
CC
+ 0.3V)
-0.3V ~ (V
CC
+ 0.3V)
-0.3V ~ (V
CC
+ 0.3V)
+125
°C
-55
°C
~ +150
°C
+260
°C
/ 10sec.
2.1W
1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Charac-
teristics” specify conditions for device operation.
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THine Electronics, Inc.
THC63LVD103D _Rev.3.0_E
Electrical Characteristics
CMOS/TTL DC Specifications
V
CC
= 3.0V ~ 3.6V, Ta = 0
°C
~ +70
°C
Symbol
V
IH
V
IL
V
DDQ1
V
REF
V
SH2
V
SL2
I
INC
Parameter
High Level Input Voltage
Low Level Input Voltage
Small Swing Voltage
Input Reference Voltage
Small Swing High Level
Input Voltage
Small Swing Low Level
Input Voltage
Input Current
Small Swing (RS=V
DDQ
/2)
V
REF
= V
DDQ
/2
V
REF
= V
DDQ
/2
0V
≤
V IN
≤
V CC
V
DDQ
/2
+100mV
V
DDQ
/2
-100mV
±
10
Conditions
RS=VCC or GND
RS=VCC or GND
Min.
2.0
GND
1.2
V
DDQ
/2
V
V
μA
Typ.
Max.
V
CC
0.8
2.8
Units
V
V
V
Notes:
1
V
DDQ
voltage defines max voltage of small swing input. It is not an actual input voltage.
2
Small swing signal is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0], TE[6:0] and CLKIN.
LVDS Transmitter DC Specifications
V
CC
= 3.0V ~ 3.6V, Ta = 0
°C
~ +70
°C
Symbol
Parameter
Conditions
Normal swing
RS=VCC
VOD
Differential Output Voltage
RL=100Ω
Reduced
swing
RS=GND
ΔVOD
VOC
ΔVOC
I
OS
I
OZ
Change in VOD between
complementary output states
Common Mode Voltage
Change in VOC between
complementary output states
Output Short Circuit Current
Output TRI-STATE Current
VOUT=0V, RL=100Ω
/PDWN=0V,
V
OUT
=0V to VCC
RL=100Ω
1.125
1.25
35
1.375
35
-24
±
10
mV
V
mV
mA
μA
Min.
250
Typ.
350
Max.
450
Units
mV
100
200
300
mV
Copyright©2011 THine Electronics, Inc.
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THine Electronics, Inc.
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