THC63LVD1027_Rev.2.0_E
THC63LVD1027
85MHz 10Bits Dual LVDS Repeater
General Description
The THC63LVD1027 LVDS(Low Voltage Differential
Signaling) repeater is designed to support pixel data
transmission between Host and Flat Panel Display up to
WUXGA resolution.
THC63LVD1027 receives the dual channel LVDS data
streams and transmits the LVDS data through various
line rate conversion modes, Dual Link Input / Dual Link
Output, Single Link Input / Dual Link Output, and Dual
Link Input / Single Link Output.
At a transmit clock frequency of 85MHz, 30bits of RGB
data and 5bits of timing and control data (HSYNC,
VSYNC, DE) are transmitted at an effective rate of
595Mbps per LVDS channel.
Features
•
•
•
•
•
•
Up to 85MHz 10bit dual channel LVDS Receiver
Up to 85MHz 10bit dual channel LVDS Transmitter
Wide LVDS input skew margin: ± 480ps at 75MHz
Accurate LVDS output timing: ± 250ps at 75MHz
Reduced swing LVDS output mode supported to
suppress the system EMI
Various line rate conversion modes supported
Dual link input / Dual link output [clkout=1x clkin]
Single link input / Dual link output [clkout=1/2x clkin]
Dual link input / Single link output [clkout=2x clkin]
•
•
•
•
•
Distribution
(signal duplication)
mode supported
Power down mode supported
3.3V single voltage power supply
No external components required for PLLs
64pin TSSOP with Exposed PAD
(0.5mm lead pitch)
Block Diagram
Dual In / Dual Out Mode
THine
®
THC63LVD1027
85MHz
85MHz
THC63LVD1027
85MHz
85MHz
10bit Pixel
LVDS-Rx
De-Serialize
LVDS-Tx
Serialize
10bit Pixel
Distribution Mode
85MHz
THC63LVD1027
85MHz
LVDS
1st Link
85MHz Max
Clock
LVDS
1st Link
PLL
Inter-Link
Multiplex
&
De-Multi-
plex
PLL
85MHz Max
Clock
85MHz
Single In / Dual Out Mode
Clock
Clock
PLL
85MHz
THC63LVD1027
42.5MHz
LVDS
2nd Link
85MHz Max
10bit Pixel
LVDS
2nd Link
85MHz Max
LVDS-Rx
De-Serialize
LDO
Regulator
LVDS-Tx
Serialize
10bit Pixel
42.5MHz
Dual In / Single Out Mode
42.5MHz
42.5MHz
THC63LVD1027
85MHz
3.3v Power Supply
Decoupling Capacitor
Copyright©2010 THine Electronics, Inc.
1/22
THine Electronics,Inc.
THC63LVD1027_Rev.2.0_E
Pin Out
RS
CAP
GND
VDD
RA1–
RA1+
RB1–
RB1+
RC1–
RC1+
RCLK1–
RCLK1+
RD1–
RD1+
RE1–
RE1+
RA2–
RA2+
RB2–
RB2+
RC2–
RC2+
RCLK2–
RCLK2+
RD2–
RD2+
RE2–
RE2+
VDD
GND
CAP
PD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
65
GND (Exposed PAD)
64
63
62
61
60
59
58
57
56
55
54
53
52
GND
CAP
GND
VDD
TA1–
TA1+
TB1–
TB1+
TC1–
TC1+
TCLK1–
TCLK1+
TD1–
TD1+
TE1–
TE1+
TA2–
TA2+
TB2–
TB2+
TC2–
TC2+
TCLK2–
TCLK2+
TD2–
TD2+
TE2–
TE2+
VDD
GND
MODE1
MODE0
TSSOP64
Exposed PAD
Top View
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Copyright©2010 THine Electronics, Inc.
2/22
THine Electronics,Inc.
THC63LVD1027_Rev.2.0_E
Pin Description
Pin Name
RA1+/–
RB1+/–
RC1+/–
RD1+/–
RE1+/–
RCLK1+/–
RA2+/–
RB2+/–
RC2+/–
RD2+/–
RE2+/–
RCLK2+/–
TA1+/–
TB1+/–
TC1+/–
TD1+/–
TE1+/–
TCLK1+/–
TA2+/–
TB2+/–
TC2+/–
TD2+/–
TE2+/–
TCLK2+/-
PD
Output
Input
Direction
Type
Description
LVDS data input for channel A of 1st Link
LVDS data input for channel B of 1st Link
LVDS data input for channel C of 1st Link
LVDS data input for channel D of 1st Link
LVDS data input for channel E of 1st Link
LVDS clock input for 1st Link
LVDS data input for channel A of 2nd Link
LVDS data input for channel B of 2nd Link
LVDS data input for channel C of 2nd Link
LVDS data input for channel D of 2nd Link
LVDS data input for channel E of 2nd Link
LVDS clock input for 2nd Link
LVDS
In Distribution and Single-in/Dual-out mode, RCLK2+/- must be Hi-Z.
(see “Mode
selection”
below in this page.)
LVDS data output for channel A of 1st Link
LVDS data output for channel B of 1st Link
LVDS data output for channel C of 1st Link
LVDS data output for channel D of 1st Link
LVDS data output for channel E of 1st Link
LVDS clock output for 1st Link
LVDS data output for channel A of 2nd Link
LVDS data output for channel B of 2nd Link
LVDS data output for channel C of 2nd Link
LVDS data output for channel D of 2nd Link
LVDS data output for channel E of 2nd Link
LVDS clock output for 2nd Link
Power Down
H: Normal operation
L: Power down state, all LVDS output signals turn to Hi-Z
LVDS output swing level selection
RS
H: Normal swing
L: Reduced swing
Mode selection
Input
MODE1
MODE0
LV-TTL
MODE1
L
L
H
L
H
MODE0
L
L
L
H
H
RCLK2+/-
clkin
Hi-Z
Hi-Z
clkin
-
Description
Dual-in / Dual-out mode
Distribution mode
Single-in / Dual-out mode
Dual-in / Single-out mode
Reserved
In Distribution and Single-in/Dual-out mode, RCLK2+/- must be Hi-Z.
VDD
GND
Power
CAP
—
3.3v power supply pins
Ground pins (Exposed PAD is also Ground)
Decoupling capacitor pins
These pins should be connected to external decoupling capacitors (C
CAP
).
Recommended
C
CAP
is 0.1uF
Copyright©2010 THine Electronics, Inc.
3/22
THine Electronics,Inc.
THC63LVD1027_Rev.2.0_E
Mode Setting
MODE1
Input/Output
RCLK2+/-
(Input mode)
H: Single
L: Dual
Dual-In/Dual-Out
(Fig.2-1, 3-1)
Distribution
(Fig.2-2, 3-2)
Single-In/Dual-Out
(Fig.2-3, 3-3)
Dual-In/Single-Out
(Fig.2-4, 3-4)
Reserved
CLK in
Hi-z
Hi-z
CLK in
--
L
L
H
L
H
MODE0
(Output mode)
H: Single
L: Dual
L
L
L
H
H
Signal Flow for Each Setting
Dual-In / Dual-Out
Distribution mode
RA1+/-
RB1+/-
RC1+/-
RD1+/-
DATA Rate RE1+/-
f
RCLK1+/-
CLK
Frequency
f
TA1+/-
CLK
TB1+/-
Frequency
TC1+/-
f
TD1+/-
TE1+/-
DATA Rate
TCLK1+/-
f
RA1+/-
RB1+/-
RC1+/-
RD1+/-
DATA Rate RE1+/-
f
RCLK1+/-
CLK
Frequency
f
Same Data
TA1+/-
CLK
TB1+/-
Frequency
TC1+/-
f
TD1+/-
TE1+/-
DATA Rate
TCLK1+/-
f
RA2+/-
RB2+/-
RC2+/-
RD2+/-
DATA Rate RE2+/-
f
RCLK2+/-
CLK
Frequency
f
TA2+/-
CLK
TB2+/-
Frequency
TC2+/-
f
TD2+/-
TE2+/-
DATA Rate
TCLK2+/-
f
=TCLK1+/-
Hi-z
Must be
Hi-z
RA2+/-
RB2+/-
RC2+/-
RD2+/-
RE2+/-
RCLK2+/-
TA2+/-
CLK
TB2+/-
Frequency
TC2+/-
f
TD2+/-
TE2+/-
DATA Rate
TCLK2+/-
f
=TCLK1+/-
Fig2-1
Single-In / Dual-Out
Fig2-2
Dual-In / Single-Out
RA1+/-
RB1+/-
RC1+/-
RD1+/-
DATA Rate RE1+/-
f
RCLK1+/-
CLK
Frequency
f
TA1+/-
CLK
TB1+/-
Frequency
TC1+/-
f/2
TD1+/-
TE1+/-
DATA Rate
TCLK1+/-
f/2
RA1+/-
RB1+/-
RC1+/-
RD1+/-
DATA Rate RE1+/-
f
RCLK1+/-
CLK
Frequency
f
TA1+/-
CLK
TB1+/-
Frequency
TC1+/-
2f
TD1+/-
TE1+/-
DATA Rate
TCLK1+/-
2f
Hi-z
Must be
Hi-z
RA2+/-
RB2+/-
RC2+/-
RD2+/-
RE2+/-
RCLK2+/-
TA2+/-
CLK
TB2+/-
Frequency
TC2+/-
f/2
TD2+/-
TE2+/-
DATA Rate
TCLK2+/-
f/2
RA2+/-
RB2+/-
RC2+/-
RD2+/-
DATA Rate RE2+/-
f
RCLK2+/-
CLK
Frequency
f
TA2+/-
TB2+/-
TC2+/-
TD2+/-
TE2+/-
TCLK2+/-
Hi-z
Fig2-3
Fig2-4
Copyright©2010 THine Electronics, Inc.
4/22
THine Electronics,Inc.
THC63LVD1027_Rev.2.0_E
Output Control / Fail Safe
THC63LVD1027 has a function to control output depending on LVDS input condition.
PD
L
H
H
H
RCLK1+/-
*
Hi-z
CLK in
CLK in
RCLK2+/-
*
*
CLK in
Hi-z
Output
All Hi-z
All Hi-z
Refer to p.4 Mode Setting #
Refer to p.4 Mode Setting #
*: Don’t care
#: If a particular input data pair is Hi-z, the corresponding output data become L according to LVDS DC spec.
For fail-safe purpose, all LVDS input pins are connected to VDD via resistance for detecting state of Hi-z.
VDD
LVDS input buffer
Internal circuit of THC63LVD1027
Copyright©2010 THine Electronics, Inc.
5/22
THine Electronics,Inc.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
