NC7WZ132 — TinyLogic
®
UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs
March 2008
NC7WZ132
TinyLogic
®
UHS Dual 2-Input NAND Gate with Schmitt
Trigger Inputs
Features
■
Space saving US8 surface mount package
■
MicroPak™ leadless package
■
Ultra High Speed; t
PD
3.1ns typ. into 50pF at 5V V
CC
■
High Output Drive; ±24mA at 3V V
CC
■
Broad V
CC
Operating Range; 1.65V to 5.5V
■
Matches the performance of LCX when operated at
■
■
■
■
General Description
The NC7WZ132 is a dual 2-Input NAND Gate from
Fairchild's Ultra High Speed Series of TinyLogic
®
. The
device is fabricated with advanced CMOS technology to
achieve ultra high speed with high output drive while
maintaining low static power dissipation over a broad
V
CC
operating range. The device is specified to operate
over the 1.65V to 5.5V V
CC
operating range. The inputs
and output are high impedance when V
CC
is 0V. Inputs
tolerate voltages up to 7V independent of V
CC
operating
voltage. Schmitt trigger inputs achieve typically 1V hys-
teresis between the positive-going and negative-going
input threshold voltage at 5V V
CC
.
3.3V V
CC
Power down high impedance inputs/output
Overvoltage tolerant inputs facilitate 5V to 3V
translation
P
roprietary
noise/EMI reduction circuitry implemented
Schmitt trigger inputs are tolerant of slow changing
input signals
Ordering Information
Order
Number
NC7WZ132K8X
NC7WZ132L8X
Package
Number
MAB08A
MAC08A
Product Code
Top Mark
WZD2
T5
Package Description
8-Lead US8, JEDEC MO-187,
Variation CA 3.1mm Wide
8-Lead MicroPak, 1.6 mm Wide
Supplied As
3k Units on Tape and
Reel
5k Units on Tape and
Reel
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2000 Fairchild Semiconductor Corporation
NC7WZ132 Rev. 1.11.0
www.fairchildsemi.com
NC7WZ132 — TinyLogic
®
UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs
Connection Diagram
Logic Symbol
IEEE/IEC
(
Top View)
Pin One Orientation Diagram
Function Table
Y
=
AB
Inputs
A
B
L
H
L
H
L
L
H
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
Output
Y
H
H
H
L
(Top View)
AAA
Pin One
AAA represents Product Code Top Mark – see ordering
code
Note:
Orientation of Top Mark determines Pin One
location. Read the top product code mark left to right,
Pin One is the lower left pin (see diagram).
Pad Assignments for MicroPak
(Top Thru View)
Pin Description
Pin Names
A
n
, B
n
Y
n
Description
Inputs
Output
©2000 Fairchild Semiconductor Corporation
NC7WZ132 Rev. 1.11.0
www.fairchildsemi.com
2
NC7WZ132 — TinyLogic
®
UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
/I
GND
T
STG
T
J
T
L
P
D
Supply Voltage
DC Input Voltage
DC Output Voltage
Parameter
Rating
–0.5V to +7V
–0.5V to +7V
–0.5V to +7V
–50mA
–50mA
±50mA
±100mA
–65°C to +150°C
150°C
260°C
250mW
DC Input Diode Current @ V
IN
<
–0.5V
DC Output Diode Current @ V
OUT
<
–0.5V
DC Output Current
DC V
CC
/GND Current
Storage Temperature
Junction Temperature Under Bias
Junction Lead Temperature (Soldering, 10 seconds)
Power Dissipation @ +85°C
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
T
A
θ
JA
Supply Voltage Operating
Parameter
Supply Voltage Data Retention
Input Voltage
Output Voltage
Operating Temperature
Thermal Resistance
Rating
1.65V to 5.5V
1.5V to 5.5V
0V to 5.5V
0V to V
CC
–40°C to +85°C
250°C/W
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©2000 Fairchild Semiconductor Corporation
NC7WZ132 Rev. 1.11.0
www.fairchildsemi.com
3
NC7WZ132 — TinyLogic
®
UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs
DC Electrical Characteristics
T
A
=
+25°C
Symbol
V
P
T
A
=
–40°C
to +85°C
Min.
0.6
1.0
1.3
1.9
2.2
0.2
0.4
0.6
1.0
1.2
0.15
0.25
0.4
0.6
0.7
1.55
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
Parameter
Positive Threshold
Voltage
V
CC
(V)
1.65
2.3
3.0
4.5
5.5
Conditions
Min.
0.6
1.0
1.3
1.9
2.2
0.2
0.4
0.6
1.0
1.2
0.15
0.25
0.4
0.6
0.7
Typ. Max.
0.99
1.39
1.77
2.49
2.96
0.53
0.78
1.02
1.48
1.76
0.46
0.61
0.75
1.01
1.20
1.65
2.3
3.0
4.5
1.52
2.15
2.80
2.68
4.20
0.0
0.0
0.0
0.0
0.10
0.10
0.10
0.10
0.24
0.3
0.4
0.55
0.55
±0.1
1
1
1.4
1.8
2.2
3.1
3.6
0.9
1.15
1.5
2.0
2.3
0.9
1.1
1.2
1.5
1.7
Max. Units
1.4
1.8
2.2
3.1
3.6
0.9
1.15
1.5
2.0
2.3
0.9
1.1
1.2
1.5
1.7
V
V
V
V
V
N
Negative Threshold
Voltage
1.65
2.3
3.0
4.5
5.5
V
H
Hysteresis Voltage
1.65
2.3
3.0
4.5
5.5
V
OH
HIGH Level Output
Voltage
1.65
2.3
3.0
4.5
1.65
2.3
3.0
3.0
4.5
V
IN
=
V
IL
I
OH
=
–100µA
1.55
2.2
2.9
4.4
I
OH
=
–4mA
I
OH
=
–8mA
I
OH
=
–16mA
I
OH
=
–24mA
I
OH
=
–32mA
V
IN
=
V
IH
I
OL
=
100µA
1.29
1.9
2.4
2.3
3.8
V
OL
LOW Level Output
Voltage
1.65
2.3
3.0
4.5
1.65
2.3
3.0
3.0
4.5
0.10
0.10
0.10
0.10
0.24
0.3
0.4
0.55
0.55
±1
10
10
V
I
OL
=
4mA
I
OL
=
8mA
I
OL
=
16mA
I
OL
=
24mA
I
OL
=
32mA
V
IN
=
5.5V, GND
V
IN
or V
OUT
=
5.5V
0.08
0.10
0.15
0.22
0.22
I
IN
I
OFF
I
CC
Input Leakage
Current
Power Off
Leakage Current
Quiescent Supply
Current
0 to 5.5
0.0
µA
µA
µA
1.65 to 5.5 V
IN
=
5.5V, GND
©2000 Fairchild Semiconductor Corporation
NC7WZ132 Rev. 1.11.0
www.fairchildsemi.com
4
NC7WZ132 — TinyLogic
®
UHS Dual 2-Input NAND Gate with Schmitt Trigger Inputs
AC Electrical Characteristics
T
A
=
+25°C
Symbol
t
PLH
, t
PHL
T
A
=
–40°C
to +85°C
Min.
3.0
2.0
1.2
0.8
1.8
1.2
Parameter
Propagation Delay
V
CC
(V)
Conditions
Min.
3.0
2.0
1.2
0.8
Typ.
7.1
4.5
3.4
2.6
4.0
3.1
2.5
15
18
Max.
13.0
7.5
5.0
3.8
5.8
4.5
Max.
13.5
8.0
5.5
4.2
6.3
4.9
Units
ns
Figure
Number
Figure 1
Figure 3
1.8 ± 0.15 C
L
=
15 pF,
2.5 ± 0.2 R
L
=
1MΩ
3.3 ± 0.3
5.0 ± 0.5
t
PLH,
t
PHL
C
IN
C
PD
Propagation Delay
Input Capacitance
Power Dissipation
Capacitance
3.3 ± 0.3
5.0 ± 0.5
0
3.3
5.0
C
L
=
50pF,
R
L
=
500Ω
(2)
1.8
1.2
ns
pF
pF
Figure 1
Figure 3
Figure 2
Note:
2. C
PD
is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current
consumption (I
CCD
) at no output loading and operating at 50% duty cycle. (See Figure 2.) C
PD
is related to I
CCD
dynamic operating current by the expression: I
CCD
=
(C
PD
)(V
CC
)(f
IN
) +(I
CC
static).
AC Loading and Waveforms
C
L
includes load and stray capacitance
Input PRR
=
1.0 MHz; t
w
=
500ns
Figure 1. AC Test Circuit
Figure 3. AC Waveforms
Input
=
AC Waveform; t
r
=
t
f
=
1.8ns;
PRR
=
10 MHz;Duty Cycle
=
50%
Figure 2. I
CCD
Test Circuit
©2000 Fairchild Semiconductor Corporation
NC7WZ132 Rev. 1.11.0
www.fairchildsemi.com
5
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